| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/edma4/ |
| D | fsl_edma_core.h | 216 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
233 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma4/ |
| D | fsl_edma_core.h | 216 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
233 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K142W_LPTMR.h | 73 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
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| D | S32K142_LPTMR.h | 73 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
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| D | S32K144W_LPTMR.h | 73 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
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| D | S32K118_LPTMR.h | 73 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
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| D | S32K116_LPTMR.h | 73 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
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| D | S32K148_LPTMR.h | 73 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
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| D | S32K144_LPTMR.h | 73 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
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| D | S32K146_LPTMR.h | 73 …__IO uint32_t CSR; /**< Low Power Timer Control Status Register, off… member
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| D | S32K116_SCG.h | 76 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ member
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| D | S32K118_SCG.h | 76 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ member
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| D | S32K142W_SCG.h | 76 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ member
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| D | S32K144W_SCG.h | 76 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ member
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| D | S32K142_SCG.h | 76 __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ member
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_EDMA4_MP.h | 76 …__IO uint32_t CSR; /**< Management Page Control Register, offset: 0x… member
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| D | S32Z2_FEED_DMA_MP.h | 76 __IO uint32_t CSR; /**< Management Page Control, offset: 0x0 */ member
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| D | S32Z2_RESULT_DMA_MP.h | 76 __IO uint32_t CSR; /**< Management Page Control, offset: 0x0 */ member
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| D | S32Z2_EDMA3_MP.h | 76 __IO uint32_t CSR; /**< Management Page Control, offset: 0x0 */ member
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| D | S32Z2_EDMA3_TCD.h | 98 …__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x3C, … member
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| D | S32Z2_FEED_DMA_TCD.h | 98 …__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x3C, … member
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_DMA.h | 76 __IO uint32_t CSR; /**< Management Page Control, offset: 0x0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma/ |
| D | fsl_edma.h | 215 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/dma3/ |
| D | fsl_ad_edma.h | 228 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
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| D | fsl_edma.h | 229 __IO uint16_t CSR; /*!< CSR register, for TCD control status */ member
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