1# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
2# SPDX-License-Identifier: Apache-2.0
3
4if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
5
6ESP32_PSRAM0_NODE_PATH := $(dt_nodelabel_path,psram0)
7
8config ESP_SPIRAM
9	bool "Support for external, SPI-connected RAM"
10	default n if MCUBOOT
11	default n if ESP32_USE_UNSUPPORTED_REVISION && SOC_SERIES_ESP32
12	select SHARED_MULTI_HEAP
13	help
14	  This enables support for an external SPI RAM chip, connected in
15	  parallel with the main SPI flash chip.
16
17menu "SPI RAM config"
18	depends on ESP_SPIRAM
19
20config ESP_SPIRAM_HEAP_SIZE
21	int "Size of SPIRAM heap"
22	default 262134 if SYS_HEAP_SMALL_ONLY
23	default 1048576 if !SYS_HEAP_SMALL_ONLY
24	help
25	  Specify size of SPIRAM heap.
26
27config ESP_SPIRAM_MEMTEST
28	bool "Run memory test on SPI RAM initialization"
29	default y
30	help
31	  Runs a memory test on initialization. Disable this for faster startup.
32
33choice SPIRAM_MODE
34	prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
35	default SPIRAM_MODE_QUAD
36
37	config SPIRAM_MODE_QUAD
38		bool "Quad Mode PSRAM"
39
40	config SPIRAM_MODE_OCT
41		bool "Octal Mode PSRAM"
42		depends on SOC_SERIES_ESP32S3
43
44endchoice # SPIRAM_MODE
45
46choice SPIRAM_TYPE
47	prompt "Type of SPI RAM chip in use"
48	default SPIRAM_TYPE_ESPPSRAM16 if SPIRAM_MODE_QUAD
49	default SPIRAM_TYPE_ESPPSRAM64
50
51config SPIRAM_TYPE_ESPPSRAM16
52	bool "ESP-PSRAM16 or APS1604"
53	depends on SPIRAM_MODE_QUAD && (ESP_SPIRAM_SIZE = 2097152)
54
55config SPIRAM_TYPE_ESPPSRAM32
56	bool "ESP-PSRAM32 or IS25WP032"
57	depends on SPIRAM_MODE_QUAD && (ESP_SPIRAM_SIZE = 4194304)
58
59config SPIRAM_TYPE_ESPPSRAM64
60	bool "ESP-PSRAM64, LY68L6400 or APS6408"
61	depends on (ESP_SPIRAM_SIZE = 8388608)
62
63endchoice # SPIRAM_TYPE
64
65config ESP_SPIRAM_SIZE
66	int "Size of SPIRAM part"
67	default $(dt_node_int_prop_int,$(ESP32_PSRAM0_NODE_PATH),size) if $(dt_nodelabel_enabled,psram0)
68	default 0
69	help
70	  Specify size of SPIRAM part.
71	  NOTE: In ESP32, if SPIRAM size is greater than 4MB,
72	  only lower 4MB can be allocated using k_malloc().
73
74choice SPIRAM_SPEED
75	prompt "Set RAM clock speed"
76	default SPIRAM_SPEED_40M
77	help
78	  Select the speed for the SPI RAM chip.
79
80config SPIRAM_SPEED_20M
81	bool "20MHz clock speed"
82	depends on SOC_SERIES_ESP32S2
83
84config SPIRAM_SPEED_26M
85	bool "26MHz clock speed"
86	depends on SOC_SERIES_ESP32S2
87
88config SPIRAM_SPEED_40M
89	bool "40MHz clock speed"
90
91config SPIRAM_SPEED_80M
92	bool "80MHz clock speed"
93	depends on ESPTOOLPY_FLASHFREQ_80M
94
95config SPIRAM_SPEED_120M
96	bool "120MHz clock speed"
97	depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3
98
99endchoice # SPIRAM_SPEED
100
101config SPIRAM_SPEED
102	int
103	default 120 if SPIRAM_SPEED_120M
104	default 80 if SPIRAM_SPEED_80M
105	default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M
106
107config SPIRAM_CLK_IO
108	int
109	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
110	default 30
111
112config SPIRAM_CS_IO
113	int
114	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
115	default 26
116
117config SPIRAM_FETCH_INSTRUCTIONS
118	bool "Move Instructions in Flash to PSRAM"
119	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
120	default n
121	help
122	  If enabled, instructions in flash will be moved into PSRAM on startup.
123	  If SPIRAM_RODATA is also enabled, code that requires execution during an SPI1 Flash operation
124	  can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
125	  for more details).
126
127config SPIRAM_RODATA
128	bool "Move Read-Only Data in Flash to PSRAM"
129	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
130	default n
131	help
132	  If enabled, rodata in flash will be moved into PSRAM on startup.
133	  If SPIRAM_FETCH_INSTRUCTIONS is also enabled, code that requires execution during an SPI1 Flash operation
134	  can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
135	  for more details).
136
137config SPIRAM_ECC_ENABLE
138	bool "Allow enabling SPI RAM ECC"
139	default n
140	depends on SPIRAM_MODE_OCT && SOC_SERIES_ESP32S3
141	help
142	  Enable MSPI Error-Correcting Code function when accessing SPIRAM.
143	  If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
144
145if SOC_SERIES_ESP32
146
147menu "PSRAM clock and cs IO for ESP32-DOWD"
148
149config D0WD_PSRAM_CLK_IO
150	int "PSRAM CLK IO number"
151	range 0 33
152	default 17
153	help
154	  The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
155	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
156
157config D0WD_PSRAM_CS_IO
158	int "PSRAM CS IO number"
159	range 0 33
160	default 16
161	help
162	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
163	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
164
165endmenu # PSRAM clock and cs IO for ESP32-DOWD
166
167menu "PSRAM clock and cs IO for ESP32-D2WD"
168
169config D2WD_PSRAM_CLK_IO
170	int "PSRAM CLK IO number"
171	range 0 33
172	default 9
173	help
174	  User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
175	  so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
176
177config D2WD_PSRAM_CS_IO
178	int "PSRAM CS IO number"
179	range 0 33
180	default 10
181	help
182	  User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
183	  so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
184
185endmenu # PSRAM clock and cs IO for ESP32-D2WD
186
187menu "PSRAM clock and cs IO for ESP32-PICO"
188
189config PICO_PSRAM_CS_IO
190	int "PSRAM CS IO number"
191	range 0 33
192	default 10
193	help
194	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
195
196	  For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
197	  IO For the reference hardware design, please refer to
198	  https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
199
200endmenu # PSRAM clock and cs IO for ESP32-PICO
201
202config SPIRAM_CUSTOM_SPIWP_SD3_PIN
203	bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
204	depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
205	default n
206	help
207	  This setting is only used if the SPI flash pins have been overridden by setting the eFuses
208	  SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
209
210	  When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
211	  ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
212	  mode, so a WP pin setting is necessary.
213
214	  If this config item is set to N (default), the correct WP pin will be automatically used for any
215	  Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
216	  to Y and specify the GPIO number connected to the WP pin.
217
218	  When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
219	  configured in the bootloader.
220
221config SPIRAM_SPIWP_SD3_PIN
222	int "Custom SPI PSRAM WP(SD3) Pin"
223	depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN
224	range 0 33
225	default 7
226	help
227	  The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
228
229	  If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
230	  value to the GPIO number of the SPIRAM WP pin.
231
232endif # SOC_SERIES_ESP32
233
234endmenu # ESP_SPIRAM
235
236endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
237