1# Copyright 2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_FAMILY_NXP_IMXRT
5	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
6
7if SOC_FAMILY_NXP_IMXRT
8
9# Source series Kconfig files first, so SOCs
10# can override the defaults given here
11rsource "*/Kconfig"
12
13rsource "../common/Kconfig.flexspi_xip"
14
15# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
16# should be set elsewhere, since the determination of which SOC core
17# requires the boot header is SOC specific.
18config NXP_IMXRT_BOOT_HEADER
19	bool "Boot header"
20	default y
21	depends on !(BOOTLOADER_MCUBOOT || SECOND_CORE_MCUX)
22	help
23	  Enable data structures required by the boot ROM to boot the
24	  application from an external flash device.
25
26if NXP_IMXRT_BOOT_HEADER
27
28rsource "../common/Kconfig.rom_loader"
29
30choice BOOT_DEVICE
31	prompt "Boot device"
32	default BOOT_FLEXSPI_NOR
33
34config BOOT_FLEXSPI_NOR
35	bool "FlexSPI serial NOR"
36	depends on HAS_MCUX_FLEXSPI
37
38config BOOT_FLEXSPI_NAND
39	bool "FlexSPI serial NAND"
40	depends on HAS_MCUX_FLEXSPI
41
42config BOOT_SEMC_NOR
43	bool "SEMC parallel NOR"
44	depends on HAS_MCUX_SEMC
45
46config BOOT_SEMC_NAND
47	bool "SEMC parallel NAND"
48	depends on HAS_MCUX_SEMC
49
50endchoice # BOOT_DEVICE
51
52config FLEXSPI_CONFIG_BLOCK_OFFSET
53	hex "FlexSPI config block offset"
54	default 0x0 if BOOT_FLEXSPI_NOR
55	default 0x400
56	help
57	  FlexSPI configuration block consists of parameters regarding specific
58	  flash devices including read command sequence, quad mode enablement
59	  sequence (optional), etc. The boot ROM expects FlexSPI configuration
60	  parameter to be presented in serial nor flash.
61
62config IMAGE_VECTOR_TABLE_OFFSET
63	hex "Image vector table offset"
64	default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
65	default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
66	help
67	  The Image Vector Table (IVT) provides the boot ROM with pointers to
68	  the application entry point and device configuration data. The boot
69	  ROM requires a fixed IVT offset for each type of boot device.
70
71config DEVICE_CONFIGURATION_DATA
72	bool "Device configuration data"
73	help
74	  Device configuration data (DCD) provides a sequence of commands to
75	  the boot ROM to initialize components such as an SDRAM. This is
76	  useful if your application expects components like SDRAM to be
77	  initialized at boot time.
78
79config EXTERNAL_MEM_CONFIG_DATA
80	bool "External Memory Configuration Data"
81	depends on !DEVICE_CONFIGURATION_DATA
82	help
83	  External memory configuration data (XMDC) provides an alternative
84	  configuration sequences which allows to intilialize the external memory
85	  at the boot time. This sequence allows to configure
86	  external memories (such as SDRAM) with more advanced option.
87	  This is a new alternative boot header compared to DCD, and DCD must be disabled
88	  in order to select this option.
89
90config EXTERNAL_MEM_CONFIG_OFFSET
91	hex "External memory configuration offset"
92	depends on EXTERNAL_MEM_CONFIG_DATA
93	default 0x800 if SOC_SERIES_IMXRT118X
94	default 0x1040 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
95	help
96	  As specified by the boot ROM, the External Memory configuration data must be
97	  placed in a specific address location to be pointed by the boot ROM.
98
99endif # NXP_IMXRT_BOOT_HEADER
100
101config NXP_IMX_EXTERNAL_SDRAM
102	bool "Allow access to external SDRAM region"
103	help
104	  Enable access to external SDRAM region managed by the SEMC. This
105	  setting should be enabled when the application uses SDRAM, or
106	  an MPU region will be defined to disable cached access to the
107	  SDRAM memory space.
108
109config NXP_IMX_EXTERNAL_HYPERRAM
110	bool "Allow access to external HYPERRAM region"
111	help
112	  Enable access to external HYPERRAM region managed by the FLEXSPI.
113	  This setting should be enabled when the application uses HYPERRAM,
114	  or an MPU region will be defined to disable cached access to the
115	  HYPERRAM memory space.
116config SECOND_CORE_MCUX
117	bool "Dual core operation on the RT11xx series"
118	depends on SOC_SERIES_IMXRT11XX
119	help
120	  Indicates the second core will be enabled, and the part will run
121	  in dual core mode. Enables dual core operation on the RT11xx series,
122	  by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU.
123	  The M4 image will be loaded from flash into RAM based off a
124	  generated header specifying the VMA and LMA of each memory section
125	  to load
126
127if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
128
129config PM_MCUX_GPC
130	bool "MCUX general power controller driver"
131
132config PM_MCUX_DCDC
133	bool "MCUX dcdc converter module driver"
134
135config PM_MCUX_PMU
136	bool "MCUX power management unit driver"
137
138config DCDC_VALUE
139	hex "DCDC value for VDD_SOC"
140
141config INIT_ARM_PLL
142	bool "Initialize ARM PLL"
143
144config INIT_VIDEO_PLL
145	bool "Initialize Video PLL"
146
147config INIT_ENET_PLL
148	bool
149	help
150	  If y, the Ethernet PLL is initialized. Always enabled on e.g.
151	  MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
152	  for MIMXRT1021").
153
154config INIT_SYS_PLL
155	bool "Initialize System PLL"
156
157endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
158
159endif # SOC_FAMILY_NXP_IMXRT
160