1# Common architecture configuration options
2
3# Copyright (c) 2022, CSIRO.
4# SPDX-License-Identifier: Apache-2.0
5
6config SEMIHOST
7	bool "Semihosting support for ARM and RISC-V targets"
8	depends on ARM || ARM64 || RISCV
9	help
10	  Semihosting is a mechanism that enables code running on an ARM or
11	  RISC-V target to communicate and use the Input/Output facilities on
12	  a host computer that is running a debugger.
13	  Additional information can be found in:
14	  https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
15	  https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
16	  This option is compatible with hardware and with QEMU, through the
17	  (automatic) use of the -semihosting-config switch when invoking it.
18
19config ISR_TABLE_SHELL
20	bool "Shell command to dump the ISR tables"
21	depends on GEN_SW_ISR_TABLE
22	depends on SHELL
23	help
24	  This option enables a shell command to dump the ISR tables.
25
26
27config ARM_MPU
28	bool "ARM MPU Support"
29	select MPU
30	select SRAM_REGION_PERMISSIONS
31	select THREAD_STACK_INFO
32	select ARCH_HAS_EXECUTABLE_PAGE_BIT if (CPU_AARCH32_CORTEX_R || CPU_CORTEX_M)
33	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_SYSMPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
34	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
35	select MPU_GAP_FILLING if AARCH32_ARMV8_R
36	select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS if (CPU_AARCH32_CORTEX_R || CPU_CORTEX_M)
37	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE && CPU_AARCH64_CORTEX_R
38	default y if CPU_AARCH64_CORTEX_R
39	depends on CPU_HAS_MPU
40	help
41	  MCU implements Memory Protection Unit.
42
43	  Notes:
44	  The ARMv6-M, ARMv7-M, and ARMv8-R MPU MPU architecture requires a power-of-two
45	  alignment of MPU region base address and size.
46
47	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
48	  to have power-of-two alignment for base address and region size.
49
50	  The ARMv8-M and ARMv8-R MPU requires the active MPU regions be non-overlapping.
51	  As a result of this, both respective MPUs needs to fully partition the
52	  memory map when programming dynamic memory regions (e.g. PRIV stack
53	  guard, user thread stack, and application memory domains), if the
54	  system requires PRIV access policy different from the access policy
55	  of the ARMv8-M or ARMv8-R background memory map. The application developer may
56	  enforce full PRIV (kernel) memory partition by enabling the
57	  MPU_GAP_FILLING option.
58	  By not enforcing full partition, MPU may leave part of kernel
59	  SRAM area covered only by the default ARMv8-M or ARMv8-R memory map. This
60	  is fine for User Mode, since the background ARM map does not
61	  allow nPRIV access at all. However, since the background map
62	  policy allows instruction fetches by privileged code, forcing
63	  this Kconfig option off prevents the system from directly
64	  triggering MemManage exceptions upon accidental attempts to
65	  execute code from SRAM in XIP builds.
66	  Since this does not compromise User Mode, we make the skipping
67	  of full partitioning the default behavior for the ARMv8-M and ARMv8-R MPU
68	  driver.
69