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Searched defs:CLKDIV0 (Results 1 – 4 of 4) sorted by relevance

/hal_nuvoton-latest/m48x/Devices/M480/Include/
Dclk_reg.h993 …__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 … member
/hal_nuvoton-latest/m2l31x/Devices/M2L31/Include/
Dclk_reg.h1497 …__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 … member
Dsys_reg.h324 …__IO uint32_t CLKDIV0; /*!< [0x0060] Peripheral Clock Divider Number Register 0 … member
/hal_nuvoton-latest/m46x/Devices/M460/Include/
Dclk_reg.h1492 …__IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 … member