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Searched defs:CACHE64_POLSEL_BASE_PTRS (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6556 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL } macro
6569 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h6556 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL } macro
6569 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL } macro
DMIMXRT685S_dsp.h1209 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h3067 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
3080 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h3067 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
3080 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h7781 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
7798 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
DMIMXRT595S_dsp.h1582 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7780 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
7797 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7777 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
7794 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h3066 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
3079 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8332 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
8345 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
DMCXN546_cm33_core1.h8332 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
8345 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8332 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
8345 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
DMCXN547_cm33_core1.h8332 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
8345 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16964 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
16981 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
DMIMXRT798S_cm33_core0.h17023 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
17040 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_cm33_core0.h17023 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
17040 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
DMIMXRT735S_ezhv.h16515 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h17023 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
17040 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8366 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
8379 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
DMCXN947_cm33_core0.h8366 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
8379 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8366 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
8379 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
DMCXN946_cm33_core1.h8366 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
8379 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13579 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
13596 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h13579 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro
13596 #define CACHE64_POLSEL_BASE_PTRS { CACHE64_POLSEL0, CACHE64_POLSEL1 } macro

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