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Searched defs:CACHE64_CTRL_PHYMEM_BASES (Results 1 – 25 of 29) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6437 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u } macro
6446 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h6437 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u } macro
6446 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2949 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } macro
2958 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2949 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } macro
2958 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h7654 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } macro
7663 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7653 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } macro
7662 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7650 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } macro
7659 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2948 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } macro
2957 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8214 #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } macro
8223 #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } macro
DMCXN546_cm33_core1.h8214 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u} macro
8223 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x80000000u, 0xA0000000u} macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8214 #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } macro
8223 #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } macro
DMCXN547_cm33_core1.h8214 #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } macro
8223 #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_cm33_core0.h16898 #define CACHE64_CTRL_PHYMEM_BASES { 0x38000000u, 0x18000000u } macro
16907 #define CACHE64_CTRL_PHYMEM_BASES { 0x28000000u, 0x08000000u } macro
DMIMXRT735S_ezhv.h16409 #define CACHE64_CTRL_PHYMEM_BASES { 0x28000000u, 0x08000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_cm33_core0.h16898 #define CACHE64_CTRL_PHYMEM_BASES { 0x38000000u, 0x18000000u } macro
16907 #define CACHE64_CTRL_PHYMEM_BASES { 0x28000000u, 0x08000000u } macro
DMIMXRT798S_ezhv.h16409 #define CACHE64_CTRL_PHYMEM_BASES { 0x28000000u, 0x08000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16898 #define CACHE64_CTRL_PHYMEM_BASES { 0x38000000u, 0x18000000u } macro
16907 #define CACHE64_CTRL_PHYMEM_BASES { 0x28000000u, 0x08000000u } macro
DMIMXRT758S_ezhv.h16409 #define CACHE64_CTRL_PHYMEM_BASES { 0x28000000u, 0x08000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8248 #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } macro
8257 #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } macro
DMCXN947_cm33_core0.h8248 #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } macro
8257 #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8248 #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } macro
8257 #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } macro
DMCXN946_cm33_core1.h8248 #define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} } macro
8257 #define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13452 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } macro
13461 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h13452 #define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x38000000u } macro
13461 #define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x28000000u } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h2896 #define CACHE64_CTRL_PHYMEM_BASES { 0x00000000u, 0x20000000u } macro

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