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Searched defs:CACHE64_CTRL_CSAR_PHYADDR_MASK (Results 1 – 25 of 38) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1109 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYA… macro
DMIMXRT685S_cm33.h6451 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYA… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6451 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYA… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1478 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYA… macro
DMIMXRT595S_cm33.h7668 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYA… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2898 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2898 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7667 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYA… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7664 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYA… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2897 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8161 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
DMCXN546_cm33_core1.h8161 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8161 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
DMCXN547_cm33_core1.h8161 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16792 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
DMIMXRT798S_cm33_core0.h16835 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
DMIMXRT798S_ezhv.h16374 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16374 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
DMIMXRT735S_cm33_core0.h16835 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16835 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8195 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
DMCXN947_cm33_core0.h8195 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8195 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
DMCXN946_cm33_core1.h8195 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (0xFFFFFFFEU) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13466 #define CACHE64_CTRL_CSAR_PHYADDR_MASK (CACHE64_CTRL_CSAR_PHYADDR27_1_MASK | CACHE64_CTRL_CSAR_PHYA… macro

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