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Searched defs:CACHE64_CTRL_CCR_ENCACHE_MASK (Results 1 – 25 of 38) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h931 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMIMXRT685S_cm33.h6239 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6239 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1287 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMIMXRT595S_cm33.h7435 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2741 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2741 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7434 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7431 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2740 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h7994 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMCXN546_cm33_core1.h7994 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h7994 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMCXN547_cm33_core1.h7994 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16633 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMIMXRT798S_cm33_core0.h16676 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMIMXRT798S_ezhv.h16215 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16215 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMIMXRT735S_cm33_core0.h16676 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16676 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8028 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMCXN947_cm33_core0.h8028 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8028 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
DMCXN946_cm33_core1.h8028 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13242 #define CACHE64_CTRL_CCR_ENCACHE_MASK (0x1U) macro

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