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Searched defs:CACHE64_CTRL_BASE_PTRS (Results 1 – 25 of 38) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6420 #define CACHE64_CTRL_BASE_PTRS { CACHE64 } macro
6433 #define CACHE64_CTRL_BASE_PTRS { CACHE64 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h6420 #define CACHE64_CTRL_BASE_PTRS { CACHE64 } macro
6433 #define CACHE64_CTRL_BASE_PTRS { CACHE64 } macro
DMIMXRT685S_dsp.h1107 #define CACHE64_CTRL_BASE_PTRS { CACHE64 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2932 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
2945 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2932 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
2945 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h7633 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
7650 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
DMIMXRT595S_dsp.h1476 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7632 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
7649 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7629 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
7646 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2931 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
2944 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8195 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
8208 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
DMCXN546_cm33_core1.h8195 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
8208 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8195 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
8208 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
DMCXN547_cm33_core1.h8195 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
8208 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16834 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
16851 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
DMIMXRT798S_cm33_core0.h16877 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
16894 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_cm33_core0.h16877 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
16894 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
DMIMXRT735S_ezhv.h16407 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16877 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
16894 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8229 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
8242 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
DMCXN947_cm33_core0.h8229 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
8242 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8229 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
8242 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
DMCXN946_cm33_core1.h8229 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
8242 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13431 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
13448 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h13431 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro
13448 #define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0, CACHE64_CTRL1 } macro

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