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Searched defs:CACHE64_CTRL0_BASE (Results 1 – 25 of 35) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2922 #define CACHE64_CTRL0_BASE (0x5002E000u) macro
2939 #define CACHE64_CTRL0_BASE (0x4002E000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2922 #define CACHE64_CTRL0_BASE (0x5002E000u) macro
2939 #define CACHE64_CTRL0_BASE (0x4002E000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h7615 #define CACHE64_CTRL0_BASE (0x50033000u) macro
7640 #define CACHE64_CTRL0_BASE (0x40033000u) macro
DMIMXRT595S_dsp.h1466 #define CACHE64_CTRL0_BASE (0x40033000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7614 #define CACHE64_CTRL0_BASE (0x50033000u) macro
7639 #define CACHE64_CTRL0_BASE (0x40033000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7611 #define CACHE64_CTRL0_BASE (0x50033000u) macro
7636 #define CACHE64_CTRL0_BASE (0x40033000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2921 #define CACHE64_CTRL0_BASE (0x5002E000u) macro
2938 #define CACHE64_CTRL0_BASE (0x4002E000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8185 #define CACHE64_CTRL0_BASE (0x5001B000u) macro
8202 #define CACHE64_CTRL0_BASE (0x4001B000u) macro
DMCXN546_cm33_core1.h8185 #define CACHE64_CTRL0_BASE (0x5001B000u) macro
8202 #define CACHE64_CTRL0_BASE (0x4001B000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8185 #define CACHE64_CTRL0_BASE (0x5001B000u) macro
8202 #define CACHE64_CTRL0_BASE (0x4001B000u) macro
DMCXN547_cm33_core1.h8185 #define CACHE64_CTRL0_BASE (0x5001B000u) macro
8202 #define CACHE64_CTRL0_BASE (0x4001B000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16816 #define CACHE64_CTRL0_BASE (0x50035000u) macro
16841 #define CACHE64_CTRL0_BASE (0x40035000u) macro
DMIMXRT798S_cm33_core0.h16859 #define CACHE64_CTRL0_BASE (0x50035000u) macro
16884 #define CACHE64_CTRL0_BASE (0x40035000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_cm33_core0.h16859 #define CACHE64_CTRL0_BASE (0x50035000u) macro
16884 #define CACHE64_CTRL0_BASE (0x40035000u) macro
DMIMXRT735S_ezhv.h16397 #define CACHE64_CTRL0_BASE (0x40035000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16859 #define CACHE64_CTRL0_BASE (0x50035000u) macro
16884 #define CACHE64_CTRL0_BASE (0x40035000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8219 #define CACHE64_CTRL0_BASE (0x5001B000u) macro
8236 #define CACHE64_CTRL0_BASE (0x4001B000u) macro
DMCXN947_cm33_core0.h8219 #define CACHE64_CTRL0_BASE (0x5001B000u) macro
8236 #define CACHE64_CTRL0_BASE (0x4001B000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8219 #define CACHE64_CTRL0_BASE (0x5001B000u) macro
8236 #define CACHE64_CTRL0_BASE (0x4001B000u) macro
DMCXN946_cm33_core1.h8219 #define CACHE64_CTRL0_BASE (0x5001B000u) macro
8236 #define CACHE64_CTRL0_BASE (0x4001B000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13413 #define CACHE64_CTRL0_BASE (0x50033000u) macro
13438 #define CACHE64_CTRL0_BASE (0x40033000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h13413 #define CACHE64_CTRL0_BASE (0x50033000u) macro
13438 #define CACHE64_CTRL0_BASE (0x40033000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h2858 #define CACHE64_CTRL0_BASE (0x38046000u) macro
2883 #define CACHE64_CTRL0_BASE (0x28046000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_cm33.h2858 #define CACHE64_CTRL0_BASE (0x38046000u) macro
2883 #define CACHE64_CTRL0_BASE (0x28046000u) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/
DMIMX8UD5_cm33.h2858 #define CACHE64_CTRL0_BASE (0x38046000u) macro
2883 #define CACHE64_CTRL0_BASE (0x28046000u) macro

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