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Searched defs:CACHE64_CTRL0 (Results 1 – 25 of 35) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2926 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
2941 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2926 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
2941 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h7619 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
7642 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
DMIMXRT595S_dsp.h1468 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7618 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
7641 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7615 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
7638 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2925 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
2940 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8189 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
8204 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
DMCXN546_cm33_core1.h8189 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
8204 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8189 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
8204 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
DMCXN547_cm33_core1.h8189 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
8204 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16820 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
16843 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
DMIMXRT798S_cm33_core0.h16863 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
16886 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_cm33_core0.h16863 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
16886 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
DMIMXRT735S_ezhv.h16399 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16863 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
16886 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8223 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
8238 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
DMCXN947_cm33_core0.h8223 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
8238 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8223 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
8238 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
DMCXN946_cm33_core1.h8223 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
8238 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13417 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
13440 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h13417 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
13440 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/
DMIMX8UD3_cm33.h2862 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
2885 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/
DMIMX8UD7_cm33.h2862 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
2885 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/
DMIMX8UD5_cm33.h2862 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro
2885 #define CACHE64_CTRL0 ((CACHE64_CTRL_Type *)CACHE64_CTRL0_BASE) macro

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