Lines Matching full:mode
56 …uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to acces…
57 … quad mode on two different devices to increase the throughput.
139 used for memory-mapped mode).
146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
150 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.
154 uint32_t AddressMode; /*!< It indicates the mode of the address.
158 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.
162 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
166 …uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes ph…
168 uint32_t DataMode; /*!< It indicates the mode of the data.
171 This field is only used for indirect mode.
173 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.
179 uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
194 uint32_t LatencyMode; /*!< It configures the latency mode.
210 This field is only used for indirect mode.
212 … In case of autopolling mode, this parameter can be any value between 1 and 4 */
218 * @brief HAL OSPI Auto Polling mode configuration structure definition
235 * @brief HAL OSPI Memory Mapped mode configuration structure definition
306 … ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configur…
341 … ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */
342 … ((uint32_t)OCTOSPI_CR_DMM) /*!< Dual-Quad mode enabled */
350 … ((uint32_t)0x00000000U) /*!< Micron mode */
351 … ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */
352 … ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */
353 …AM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */
354 … ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
368 /** @defgroup OSPI_ClockMode OSPI Clock Mode
419 … /*!< Common configuration (indirect or auto-polling mode) */
420 … /*!< Read configuration (memory-mapped mode) */
421 … /*!< Write configuration (memory-mapped mode) */
422 … /*!< Wrap configuration (memory-mapped mode) */
436 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode
459 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
462 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for instru…
463 … ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruc…
468 /** @defgroup OSPI_AddressMode OSPI Address Mode
491 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
494 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for addres…
495 … ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address…
500 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
523 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
526 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for altern…
527 … ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alterna…
532 /** @defgroup OSPI_DataMode OSPI Data Mode
544 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
547 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for data p…
548 … ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data ph…
553 /** @defgroup OSPI_DQSMode OSPI DQS Mode
562 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode
580 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
592 … ((uint32_t)0x00000000U) /*!< HyperBus memory mode */
593 … ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
598 /** @defgroup OSPI_MatchMode OSPI Match Mode
601 …t32_t)0x00000000U) /*!< AND match mode between unmasked bi…
602 …nt32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bi…
629 … /*!< Timeout flag: timeout occurs in memory-mapped mode …
630 … /*!< Status match flag: received data matches in autopolling mode …
821 /* OSPI indirect mode functions */
829 /* OSPI status flag polling mode functions */
833 /* OSPI memory-mapped mode functions */
841 /* OSPI indirect mode functions */
848 /* OSPI status flag polling mode functions */
851 /* OSPI memory-mapped mode functions */
915 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ argument
916 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
931 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ argument
932 ((MODE) == HAL_OSPI_CLOCK_MODE_3))
956 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ argument
957 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
958 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
959 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
960 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
967 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ argument
968 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
970 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ argument
971 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
972 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
973 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
974 ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
981 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ argument
982 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
984 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ argument
985 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
986 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
987 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
988 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
995 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ argument
996 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
998 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ argument
999 ((MODE) == HAL_OSPI_DATA_1_LINE) || \
1000 ((MODE) == HAL_OSPI_DATA_2_LINES) || \
1001 ((MODE) == HAL_OSPI_DATA_4_LINES) || \
1002 ((MODE) == HAL_OSPI_DATA_8_LINES))
1006 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ argument
1007 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
1011 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ argument
1012 ((MODE) == HAL_OSPI_DQS_ENABLE))
1014 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ argument
1015 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
1021 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ argument
1022 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
1024 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ argument
1025 ((MODE) == HAL_OSPI_FIXED_LATENCY))
1030 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ argument
1031 ((MODE) == HAL_OSPI_MATCH_MODE_OR))
1033 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ argument
1034 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
1040 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ argument
1041 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
1047 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ argument
1048 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))