668   uint32_t tmpcr2;  in LL_TIM_HALLSENSOR_Init()  local
683   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
695   tmpcr2 |= TIM_CR2_TI1S;  in LL_TIM_HALLSENSOR_Init()
698   tmpcr2 |= LL_TIM_TRGO_OC2REF;  in LL_TIM_HALLSENSOR_Init()
721   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
852   uint32_t tmpcr2;  in OC1Config()  local
867   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
898     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);  in OC1Config()
901     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);  in OC1Config()
905   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
931   uint32_t tmpcr2;  in OC2Config()  local
946   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
977     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);  in OC2Config()
980     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);  in OC2Config()
984   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
1010   uint32_t tmpcr2;  in OC3Config()  local
1025   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
1056     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);  in OC3Config()
1059     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);  in OC3Config()
1063   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1089   uint32_t tmpcr2;  in OC4Config()  local
1104   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1135     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);  in OC4Config()
1138     MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);  in OC4Config()
1142   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()