576   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
597   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
612   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_ENCODER_Init()
613   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);  in LL_TIM_ENCODER_Init()
614   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);  in LL_TIM_ENCODER_Init()
615   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
624   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
670   uint32_t tmpccer;  in LL_TIM_HALLSENSOR_Init()  local
689   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
716   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_HALLSENSOR_Init()
717   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);  in LL_TIM_HALLSENSOR_Init()
718   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
730   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
851   uint32_t tmpccer;  in OC1Config()  local
864   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
879   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);  in OC1Config()
882   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);  in OC1Config()
892     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);  in OC1Config()
895     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);  in OC1Config()
914   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
930   uint32_t tmpccer;  in OC2Config()  local
943   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
958   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);  in OC2Config()
961   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);  in OC2Config()
971     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);  in OC2Config()
974     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);  in OC2Config()
993   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
1009   uint32_t tmpccer;  in OC3Config()  local
1022   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1037   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);  in OC3Config()
1040   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);  in OC3Config()
1050     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);  in OC3Config()
1053     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);  in OC3Config()
1072   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1088   uint32_t tmpccer;  in OC4Config()  local
1101   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1116   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);  in OC4Config()
1119   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);  in OC4Config()
1129     MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);  in OC4Config()
1132     MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);  in OC4Config()
1151   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1167   uint32_t tmpccer;  in OC5Config()  local
1181   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1190   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);  in OC5Config()
1193   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);  in OC5Config()
1212   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1228   uint32_t tmpccer;  in OC6Config()  local
1242   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1251   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);  in OC6Config()
1254   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);  in OC6Config()
1272   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()