591   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
597   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
624   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
680   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
689   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
730   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
861   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
864   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
914   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
940   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
943   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
993   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
1019   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
1022   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1072   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1098   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1101   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1151   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1178   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1181   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1212   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1239   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1242   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1272   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1295   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1303   MODIFY_REG(TIMx->CCER,  in IC1Config()
1328   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1336   MODIFY_REG(TIMx->CCER,  in IC2Config()
1361   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1369   MODIFY_REG(TIMx->CCER,  in IC3Config()
1394   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1402   MODIFY_REG(TIMx->CCER,  in IC4Config()