Lines Matching refs:Timing
318 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
324 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
325 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
326 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
327 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
328 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
329 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
330 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
331 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
336 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
337 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
338 (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | in FMC_NORSRAM_Timing_Init()
339 (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) | in FMC_NORSRAM_Timing_Init()
340 (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | in FMC_NORSRAM_Timing_Init()
341 ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | in FMC_NORSRAM_Timing_Init()
342 ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | in FMC_NORSRAM_Timing_Init()
343 Timing->AccessMode; in FMC_NORSRAM_Timing_Init()
349 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
369 … const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, in FMC_NORSRAM_Extended_Timing_Init() argument
380 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
381 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
382 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
383 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
384 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Extended_Timing_Init()
385 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Extended_Timing_Init()
389 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
390 … ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
391 … ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
392 … ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
393 … Timing->AccessMode | in FMC_NORSRAM_Extended_Timing_Init()
394 … ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); in FMC_NORSRAM_Extended_Timing_Init()
549 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_CommonSpace_Timing_Init() argument
553 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
554 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
555 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
556 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
563 Device->PMEM = (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
564 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
565 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
566 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); in FMC_NAND_CommonSpace_Timing_Init()
580 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_AttributeSpace_Timing_Init() argument
584 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
585 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
586 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
587 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
594 Device->PATT = (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
595 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
596 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
597 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); in FMC_NAND_AttributeSpace_Timing_Init()
845 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_SDRAM_Timing_Init() argument
849 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); in FMC_SDRAM_Timing_Init()
850 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); in FMC_SDRAM_Timing_Init()
851 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); in FMC_SDRAM_Timing_Init()
852 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); in FMC_SDRAM_Timing_Init()
853 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); in FMC_SDRAM_Timing_Init()
854 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); in FMC_SDRAM_Timing_Init()
855 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); in FMC_SDRAM_Timing_Init()
861 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
862 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
863 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
864 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | in FMC_SDRAM_Timing_Init()
865 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | in FMC_SDRAM_Timing_Init()
866 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) | in FMC_SDRAM_Timing_Init()
867 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); in FMC_SDRAM_Timing_Init()