Lines Matching refs:Init
190 const FMC_NORSRAM_InitTypeDef *Init) in FMC_NORSRAM_Init() argument
198 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
199 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
200 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
201 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
202 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
203 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
204 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
205 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
206 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
207 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); in FMC_NORSRAM_Init()
208 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); in FMC_NORSRAM_Init()
209 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); in FMC_NORSRAM_Init()
210 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); in FMC_NORSRAM_Init()
211 assert_param(IS_FMC_PAGESIZE(Init->PageSize)); in FMC_NORSRAM_Init()
212 assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime)); in FMC_NORSRAM_Init()
215 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
218 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) in FMC_NORSRAM_Init()
228 Init->DataAddressMux | \ in FMC_NORSRAM_Init()
229 Init->MemoryType | \ in FMC_NORSRAM_Init()
230 Init->MemoryDataWidth | \ in FMC_NORSRAM_Init()
231 Init->BurstAccessMode | \ in FMC_NORSRAM_Init()
232 Init->WaitSignalPolarity | \ in FMC_NORSRAM_Init()
233 Init->WaitSignalActive | \ in FMC_NORSRAM_Init()
234 Init->WriteOperation | \ in FMC_NORSRAM_Init()
235 Init->WaitSignal | \ in FMC_NORSRAM_Init()
236 Init->ExtendedMode | \ in FMC_NORSRAM_Init()
237 Init->AsynchronousWait | \ in FMC_NORSRAM_Init()
238 Init->WriteBurst); in FMC_NORSRAM_Init()
240 btcr_reg |= Init->ContinuousClock; in FMC_NORSRAM_Init()
241 btcr_reg |= Init->NBLSetupTime; in FMC_NORSRAM_Init()
242 btcr_reg |= Init->PageSize; in FMC_NORSRAM_Init()
262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
265 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
267 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
516 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
520 assert_param(IS_FMC_NAND_BANK(Init->NandBank)); in FMC_NAND_Init()
521 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); in FMC_NAND_Init()
522 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NAND_Init()
523 assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); in FMC_NAND_Init()
524 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); in FMC_NAND_Init()
525 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); in FMC_NAND_Init()
526 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); in FMC_NAND_Init()
529 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
531 Init->MemoryDataWidth | in FMC_NAND_Init()
532 Init->EccComputation | in FMC_NAND_Init()
533 Init->ECCPageSize | in FMC_NAND_Init()
534 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | in FMC_NAND_Init()
535 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); in FMC_NAND_Init()
786 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
790 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); in FMC_SDRAM_Init()
791 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); in FMC_SDRAM_Init()
792 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); in FMC_SDRAM_Init()
793 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_SDRAM_Init()
794 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); in FMC_SDRAM_Init()
795 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); in FMC_SDRAM_Init()
796 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); in FMC_SDRAM_Init()
797 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); in FMC_SDRAM_Init()
798 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); in FMC_SDRAM_Init()
801 if (Init->SDBank == FMC_SDRAM_BANK1) in FMC_SDRAM_Init()
805 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
806 Init->RowBitsNumber | in FMC_SDRAM_Init()
807 Init->MemoryDataWidth | in FMC_SDRAM_Init()
808 Init->InternalBankNumber | in FMC_SDRAM_Init()
809 Init->CASLatency | in FMC_SDRAM_Init()
810 Init->WriteProtection | in FMC_SDRAM_Init()
811 Init->SDClockPeriod | in FMC_SDRAM_Init()
812 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
819 (Init->SDClockPeriod | in FMC_SDRAM_Init()
820 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
824 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
825 Init->RowBitsNumber | in FMC_SDRAM_Init()
826 Init->MemoryDataWidth | in FMC_SDRAM_Init()
827 Init->InternalBankNumber | in FMC_SDRAM_Init()
828 Init->CASLatency | in FMC_SDRAM_Init()
829 Init->WriteProtection)); in FMC_SDRAM_Init()