Lines Matching refs:BTCR
262 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
267 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
295 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
300 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
303 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
335 Device->BTCR[Bank + 1U] = in FMC_NORSRAM_Timing_Init()
346 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN)) in FMC_NORSRAM_Timing_Init()
348 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
350 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
435 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Enable()
453 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Disable()