516   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
537   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
552   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_ENCODER_Init()
553   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);  in LL_TIM_ENCODER_Init()
554   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);  in LL_TIM_ENCODER_Init()
555   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
564   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
610   uint32_t tmpccer;  in LL_TIM_HALLSENSOR_Init()  local
629   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
656   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_HALLSENSOR_Init()
657   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);  in LL_TIM_HALLSENSOR_Init()
658   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
670   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
791   uint32_t tmpccer;  in OC1Config()  local
804   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
819   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);  in OC1Config()
822   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);  in OC1Config()
832     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);  in OC1Config()
835     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);  in OC1Config()
854   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
870   uint32_t tmpccer;  in OC2Config()  local
883   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
898   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);  in OC2Config()
901   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);  in OC2Config()
911     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);  in OC2Config()
914     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);  in OC2Config()
933   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
949   uint32_t tmpccer;  in OC3Config()  local
962   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
977   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);  in OC3Config()
980   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);  in OC3Config()
990     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);  in OC3Config()
993     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);  in OC3Config()
1012   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1028   uint32_t tmpccer;  in OC4Config()  local
1041   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1056   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);  in OC4Config()
1059   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);  in OC4Config()
1079   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1095   uint32_t tmpccer;  in OC5Config()  local
1109   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1118   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);  in OC5Config()
1121   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);  in OC5Config()
1140   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1156   uint32_t tmpccer;  in OC6Config()  local
1170   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1179   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);  in OC6Config()
1182   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);  in OC6Config()
1200   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()