531   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
537   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
564   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
620   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
629   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
670   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
801   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
804   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
854   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
880   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
883   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
933   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
959   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
962   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1012   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1038   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1041   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1079   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1106   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1109   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1140   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1167   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1170   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1200   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1223   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1231   MODIFY_REG(TIMx->CCER,  in IC1Config()
1256   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1264   MODIFY_REG(TIMx->CCER,  in IC2Config()
1289   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1297   MODIFY_REG(TIMx->CCER,  in IC3Config()
1322   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1330   MODIFY_REG(TIMx->CCER,  in IC4Config()