363         if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)  in HAL_DMA2D_DeInit()
380   hdma2d->Instance->FGPFCCR  =    0U;  in HAL_DMA2D_DeInit()
1029     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_EnableCLUT()
1080     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTStartLoad()
1084     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTStartLoad()
1138     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTStartLoad_IT()
1145     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTStartLoad_IT()
1198     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTLoad()
1202     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTLoad()
1258     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTLoad_IT()
1265     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTLoad_IT()
1291     reg  = &(hdma2d->Instance->FGPFCCR);  in HAL_DMA2D_CLUTLoading_Abort()
1349     reg  = &(hdma2d->Instance->FGPFCCR);  in HAL_DMA2D_CLUTLoading_Suspend()
1422       if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)  in HAL_DMA2D_CLUTLoading_Resume()
1501   layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;  in HAL_DMA2D_PollForTransfer()
1867     MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);  in HAL_DMA2D_ConfigLayer()
1932     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_ConfigCLUT()