Lines Matching refs:tmpccmr1
401 uint32_t tmpccmr1; in LL_TIM_ENCODER_Init() local
420 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); in LL_TIM_ENCODER_Init()
426 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); in LL_TIM_ENCODER_Init()
427 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); in LL_TIM_ENCODER_Init()
428 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); in LL_TIM_ENCODER_Init()
429 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); in LL_TIM_ENCODER_Init()
432 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); in LL_TIM_ENCODER_Init()
433 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); in LL_TIM_ENCODER_Init()
434 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); in LL_TIM_ENCODER_Init()
435 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); in LL_TIM_ENCODER_Init()
447 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); in LL_TIM_ENCODER_Init()
477 uint32_t tmpccmr1; in OC1Config() local
497 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); in OC1Config()
500 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); in OC1Config()
503 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); in OC1Config()
515 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); in OC1Config()
536 uint32_t tmpccmr1; in OC2Config() local
556 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); in OC2Config()
559 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); in OC2Config()
562 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); in OC2Config()
574 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); in OC2Config()