402   uint32_t tmpccer;  in LL_TIM_ENCODER_Init()  local
423   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
438   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);  in LL_TIM_ENCODER_Init()
439   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);  in LL_TIM_ENCODER_Init()
440   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);  in LL_TIM_ENCODER_Init()
441   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
450   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
478   uint32_t tmpccer;  in OC1Config()  local
491   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
506   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);  in OC1Config()
509   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);  in OC1Config()
521   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
537   uint32_t tmpccer;  in OC2Config()  local
550   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
565   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);  in OC2Config()
568   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);  in OC2Config()
580   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
596   uint32_t tmpccer;  in OC3Config()  local
609   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
624   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);  in OC3Config()
627   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);  in OC3Config()
639   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
655   uint32_t tmpccer;  in OC4Config()  local
668   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
683   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);  in OC4Config()
686   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);  in OC4Config()
698   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()