Lines Matching full:mode
54 …uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to acces…
55 … quad mode on two different devices to increase the throughput.
137 used for memory-mapped mode).
144 uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
148 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.
152 uint32_t AddressMode; /*!< It indicates the mode of the address.
156 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.
160 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
164 …uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes ph…
166 uint32_t DataMode; /*!< It indicates the mode of the data.
169 This field is only used for indirect mode.
171 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.
177 uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
192 uint32_t LatencyMode; /*!< It configures the latency mode.
208 This field is only used for indirect mode.
210 … In case of autopolling mode, this parameter can be any value between 1 and 4 */
216 * @brief HAL OSPI Auto Polling mode configuration structure definition
233 * @brief HAL OSPI Memory Mapped mode configuration structure definition
302 … ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configur…
337 … ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */
338 … ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */
346 … ((uint32_t)0x00000000U) /*!< Micron mode */
347 … ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */
348 … ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */
349 …AM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */
350 … ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
364 /** @defgroup OSPI_ClockMode OSPI Clock Mode
415 … /*!< Common configuration (indirect or auto-polling mode) */
416 … /*!< Read configuration (memory-mapped mode) */
417 … /*!< Write configuration (memory-mapped mode) */
418 … /*!< Wrap configuration (memory-mapped mode) */
432 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode
455 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
458 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for instru…
459 … ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruc…
464 /** @defgroup OSPI_AddressMode OSPI Address Mode
487 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
490 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for addres…
491 … ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address…
496 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
519 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
522 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for altern…
523 … ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alterna…
528 /** @defgroup OSPI_DataMode OSPI Data Mode
540 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
543 … ((uint32_t)0x00000000U) /*!< DTR mode disabled for data p…
544 … ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data ph…
549 /** @defgroup OSPI_DQSMode OSPI DQS Mode
558 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode
576 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
588 … ((uint32_t)0x00000000U) /*!< HyperBus memory mode */
589 … ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
594 /** @defgroup OSPI_MatchMode OSPI Match Mode
597 …t32_t)0x00000000U) /*!< AND match mode between unmasked bi…
598 …nt32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bi…
625 … /*!< Timeout flag: timeout occurs in memory-mapped mode …
626 … /*!< Status match flag: received data matches in autopolling mode …
815 /* OSPI indirect mode functions */
823 /* OSPI status flag polling mode functions */
827 /* OSPI memory-mapped mode functions */
835 /* OSPI indirect mode functions */
842 /* OSPI status flag polling mode functions */
845 /* OSPI memory-mapped mode functions */
895 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ argument
896 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
911 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ argument
912 ((MODE) == HAL_OSPI_CLOCK_MODE_3))
936 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ argument
937 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
938 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
939 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
940 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
947 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ argument
948 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
950 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ argument
951 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
952 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
953 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
954 ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
961 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ argument
962 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
964 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ argument
965 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
966 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
967 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
968 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
975 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ argument
976 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
978 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ argument
979 ((MODE) == HAL_OSPI_DATA_1_LINE) || \
980 ((MODE) == HAL_OSPI_DATA_2_LINES) || \
981 ((MODE) == HAL_OSPI_DATA_4_LINES) || \
982 ((MODE) == HAL_OSPI_DATA_8_LINES))
986 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ argument
987 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
991 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ argument
992 ((MODE) == HAL_OSPI_DQS_ENABLE))
994 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ argument
995 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
1001 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ argument
1002 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
1004 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ argument
1005 ((MODE) == HAL_OSPI_FIXED_LATENCY))
1010 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ argument
1011 ((MODE) == HAL_OSPI_MATCH_MODE_OR))
1013 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ argument
1014 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
1020 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ argument
1021 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
1027 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ argument
1028 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))