Lines Matching full:mode
54 uint32_t MemoryMode; /*!< It Specifies the memory mode.
136 used for memory-mapped mode).
142 uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
146 uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase.
150 …uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises numb…
155 uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase.
159 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
163 …uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes ph…
165 …uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of …
169 This field is only used for indirect mode.
171 uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase.
189 uint32_t LatencyMode; /*!< It configures the latency mode.
205 This field is only used for indirect mode.
207 In case of autopolling mode, this parameter can be
211 …uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of …
217 * @brief HAL XSPI Auto Polling mode configuration structure definition
236 * @brief HAL XSPI Memory Mapped mode configuration structure definition
318 …HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configur…
349 /** @defgroup XSPI_MemoryMode XSPI Memory Mode
352 #define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */
353 #define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */
362 …L_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */
363 …L_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */
364 …L_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */
365 …L_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/
366 …L_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
367 …L_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */
421 /** @defgroup XSPI_ClockMode XSPI Clock Mode
511 …PE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */
512 …PE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */
513 …PE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */
514 …PE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */
533 /** @defgroup XSPI_InstructionMode XSPI Instruction Mode
556 /** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode
559 #define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for …
560 #define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for i…
565 /** @defgroup XSPI_AddressMode XSPI Address Mode
588 /** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode
591 #define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for…
592 #define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for …
597 /** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode
620 /** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode
623 #define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for…
624 #define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for …
629 /** @defgroup XSPI_DataMode XSPI Data Mode
642 /** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode
645 #define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for …
646 #define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for d…
651 /** @defgroup XSPI_DQSMode XSPI DQS Mode
669 /** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode
681 …e HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */
682 …e HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
687 /** @defgroup XSPI_MatchMode XSPI Match Mode
690 #define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between u…
691 #define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between un…
718 … XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode …
719 …SPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode …
762 …A_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operation…
927 /* XSPI indirect mode functions */
935 /* XSPI status flag polling mode functions */
940 /* XSPI memory-mapped mode functions */
948 /* XSPI indirect mode Callback functions */
955 /* XSPI status flag polling mode functions */
958 /* XSPI memory-mapped mode functions */
1023 #define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ argument
1024 ((MODE) == HAL_XSPI_DUAL_MEM))
1071 #define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ argument
1072 ((MODE) == HAL_XSPI_CLOCK_MODE_3))
1141 #define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ argument
1142 ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \
1143 ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \
1144 ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \
1145 ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES))
1152 #define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ argument
1153 ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
1155 #define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ argument
1156 ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \
1157 ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \
1158 ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \
1159 ((MODE) == HAL_XSPI_ADDRESS_8_LINES))
1166 #define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ argument
1167 ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE))
1169 #define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ argument
1170 ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \
1171 ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \
1172 ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \
1173 ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES))
1180 #define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ argument
1181 ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE))
1183 #define IS_XSPI_DATA_MODE(TYPE,MODE) (((TYPE) == (HAL_XSPI_MEMTYPE_HYPERBUS)) ? \ argument
1184 (((MODE) == HAL_XSPI_DATA_NONE) || \
1185 ((MODE) == HAL_XSPI_DATA_8_LINES) || \
1186 ((MODE) == HAL_XSPI_DATA_16_LINES)): \
1187 (((MODE) == HAL_XSPI_DATA_NONE) || \
1188 ((MODE) == HAL_XSPI_DATA_1_LINE) || \
1189 ((MODE) == HAL_XSPI_DATA_2_LINES) || \
1190 ((MODE) == HAL_XSPI_DATA_4_LINES) || \
1191 ((MODE) == HAL_XSPI_DATA_8_LINES) || \
1192 ((MODE) == HAL_XSPI_DATA_16_LINES)))
1195 #define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ argument
1196 ((MODE) == HAL_XSPI_DATA_DTR_ENABLE))
1200 #define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ argument
1201 ((MODE) == HAL_XSPI_DQS_ENABLE))
1207 #define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ argument
1208 ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE))
1210 #define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ argument
1211 ((MODE) == HAL_XSPI_FIXED_LATENCY))
1216 #define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ argument
1217 ((MODE) == HAL_XSPI_MATCH_MODE_OR))
1219 #define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ argument
1220 ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE))
1226 #define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ argument
1227 ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE))