Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
61 …UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Tr…
62 …SecureFault_IRQn = -9, /*!< -9 Secure Fault …
63 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
64 …DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor …
65 …PendSV_IRQn = -2, /*!< -2 Pendable request for system service …
66 …SysTick_IRQn = -1, /*!< -1 System Tick Timer …
71 …RTC_IRQn = 2, /*!< RTC non-secure interrupt …
75 …FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt …
168 …CEC_IRQn = 119, /*!< CEC-HDMI global interrupt …
182 /* ------- Start of section using anonymous unions and disabling warnings ------- */
190 #pragma clang diagnostic ignored "-Wc11-extensions"
191 #pragma clang diagnostic ignored "-Wreserved-id-macro"
205 /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
218 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
250 * @brief Inter-integrated Circuit Interface
268 * @brief Improved Inter-integrated Circuit Interface
274 …t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
281 …t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */
284 …t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */
286 …t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */
292 …nt32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */
293 …t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */
296 …t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */
300 …t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */
316 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
317 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
318 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
319 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
320 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
321 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
322 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
323 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
324 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
358 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
361 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
362 …__IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */
370 __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */
395 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */
397 uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */
402 uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */
446 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
464 …__IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: …
465 …VED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
469 …VED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */
477 …VED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
478 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: …
502 …2_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */
503 …2_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
505 …2_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */
508 …2_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */
519 …__IO uint32_t NSKEYR; /*!< FLASH non-secure key register, …
522 …__IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, …
526 …__IO uint32_t NSSR; /*!< FLASH non-secure status register, …
528 …__IO uint32_t NSCR; /*!< FLASH non-secure control register, …
530 …__IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, …
534 …__IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, …
540 …*!< Reserved3, Address offset: 0x58-0x5C */
541 …__IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, …
542 …__IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, …
547 …*!< Reserved4, Address offset: 0x78-0x7C */
548 …__IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, …
549 …__IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, …
554 …*!< Reserved5, Address offset: 0x98-0x9C */
555 …__IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, …
556 …*!< Reserved6, Address offset: 0xA4-0xBF */
557 …__IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, …
558 …*!< Reserved7, Address offset: 0xC4-0xDC */
570 …< Reserved8, Address offset: 0x10C-0x19C */
571 …__IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, …
572 …< Reserved9, Address offset: 0x1A4-0x1BF */
573 …__IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, …
574 …< Reserved10, Address offset: 0x1C4-0x1DC */
593 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
598 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
600 …__IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */
610 … Reserved1, Address offset: 0x04-0x0C */
618 … Reserved3, Address offset: 0x2C-0x3C */
619 …__IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, …
620 …__IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, …
621 …__IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, …
622 …__IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, …
623 …__IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, …
624 …__IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, …
625 …__IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, …
626 …__IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, …
627 …__IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, …
628 …__IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, …
629 …__IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, …
630 …__IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, …
631 …__IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, …
632 …__IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, …
633 …__IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, …
634 …__IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, …
640 … RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
642 … RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */
643 …t32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */
644 … RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */
645 …t32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
675 …uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C …
693 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
716 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
722 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
770 …D1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
773 …D2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
779 …D5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
785 …D8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
791 …D11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
793 …D12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
795 …D13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
801 …D16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
803 …D17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
809 …D20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
811 …D21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
824 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
827 … uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
841 … uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */
942 …uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03F…
943 …__IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D…
953 * @brief Real-Time Clock
971 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
1009 …uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C …
1012 …uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC …
1071 …ESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */
1078 …ESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */
1080 …ESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */
1082 …ESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */
1084 …ESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */
1094 …ERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */
1095 …__IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset…
1122 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
1129 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
1165 …32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */
1220 …[4]; /*!< Reserved, 0x030 - 0x03C */
1229 …[8]; /*!< Reserved, 0x060 - 0x07C */
1238 …[8]; /*!< Reserved, 0x0A0 - 0x0BC */
1258 …[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
1260 …[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
1285 …BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1286 …__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, …
1294 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1344 … uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
1349 … uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
1354 … uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
1361 … uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0C4 */
1401 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1403 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1444 /* -------- End of section using anonymous unions and disabling warnings -------- */
1480 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1481 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 512 KB) non-secure base address …
1482 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address …
1483 #define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address …
1484 #define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (64 KB) non-secure base address …
1485 #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address …
1487 /* External memories base addresses - Not aliased */
1501 /* Peripheral memory map - Non secure */
1636 /* Flash, Peripheral and internal SRAMs base addresses - Secure */
1643 /* Peripheral memory map - Secure */
1783 #define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address …
1784 #define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) …
1787 #define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */
1792 #define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */
1793 #define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */
1794 #define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */
1797 #define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base a…
1802 … (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address …
1806 … (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address …
1810 … (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address …
1815 … (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address …
1819 …S (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address …
1821 …ne FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of …
1872 * Then it jumps to the non-secure reset handler present within the
1913 * @brief RSSLib Non-secure callable function pointer structure
2240 /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
3714 … ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
3739 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
3913 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data regist…
4205 …R DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
4208 … DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
4213 …R DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
4216 …RB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data…
4221 …R DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
4224 …RB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned dat…
4229 …R DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
4232 … DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
4237 …R DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
4240 …RB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data…
4245 …R DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
4248 …RB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned dat…
4253 …R DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
4256 …R DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
4261 …R DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
4264 …R DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
4269 …R DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
4272 …R DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
5066 … DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */
5069 … DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */
5072 … DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */
5075 … DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */
5078 … DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */
5081 … DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */
5084 … DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */
5087 … DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */
5118 #define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-lis…
5132 … DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag …
5158 … DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag …
5193 … DMA_CCR_ULEIE_Msk /*!< Update linked-list item error inter…
5208 #define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-lis…
5234 …k /*!< Source byte exchange within the unaligned half-word of each source w…
5257 … DMA_CTR1_DHX_Msk /*!< Destination half-word exchange …
5349 … DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */
6417 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of…
6815 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-…
6818 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-…
6979 /* HDMI-CEC (CEC) */
7036 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
7042 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
7066 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
7069 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
7077 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
7083 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
7107 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
7110 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
7121 #define FLASH_BLOCKBASED_NB_REG (1U) /*!< 1 Block-ba…
7165 … FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area inter…
7205 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-pro…
7262 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-ope…
7323 … FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */
7376 … FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option …
7379 … FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option …
7429 … FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector at…
7447 …ATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sect…
7450 …EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */
7463 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail a…
7466 … FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */
7469 …_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */
7472 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail b…
7475 …ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */
7478 …SH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */
7492 #define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail d…
7576 … FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
7583 … FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7634 … FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
7641 … FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7964 … FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
9178 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
9183 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload…
9460 …1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
9481 …2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
9496 /*----------------------------------------------------------------------------*/
9530 …3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
9551 …4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
9566 /*----------------------------------------------------------------------------*/
9595 …5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
9611 …6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
9704 …ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
9753 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
9769 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State S…
9772 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State S…
9799 …BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
9802 …K2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
10030 … LPTIM_ISR_CC1OF_Msk /*!< Capture/Compare 1 over-capture flag */
10033 … LPTIM_ISR_CC2OF_Msk /*!< Capture/Compare 2 over-capture flag */
10074 … LPTIM_ICR_CC1OCF_Msk /*!< Capture/Compare 1 over-capture clear flag */
10077 … LPTIM_ICR_CC2OCF_Msk /*!< Capture/Compare 2 over-capture clear flag */
10118 … LPTIM_DIER_CC1OIE_Msk /*!< Capture/Compare 1 over-capture interrupt ena…
10121 … LPTIM_DIER_CC2OIE_Msk /*!< Capture/Compare 2 over-capture interrupt ena…
10607 …AIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) …
10689 …LIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable …
10692 …FAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable …
10743 … SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
10821 #define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual-…
13931 /* Real-Time Clock (RTC) */
14168 …_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
15553 #define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-…
15575 #define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode…
15578 #define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode…
15581 #define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode…
15584 #define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode…
15588 …e SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */
15590 …_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation In…
15591 … (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt e…
15592 …_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt …
15593 …_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt e…
15594 …_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Inter…
15595 …_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt en…
15684 #define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Sec…
16687 … UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC de…
16690 …XFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC de…
16738 …R_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
16766 … UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
16775 … UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to…
16778 … UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to…
16825 #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role …
16854 … UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected inter…
16885 #define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role …
16926 #define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role …
16955 …LID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
16965 #define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit rece…
17047 …T_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
17056 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
17081 …T_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
17101 …DDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detec…
17145 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-…
17148 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
17153 …_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
17167 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-P…
17170 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duple…
17209 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
17266 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud …
17323 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud …
17326 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud …
17481 /* Inter-integrated Circuit Interface (I2C) */
17550 #define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Pl…
17567 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit add…
17570 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit add…
17599 …A1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
17761 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit rece…
17766 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit tran…
17771 /* Improved Inter-integrated Circuit Interface (I3C) */
17783 #define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC …
17816 #define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keepe…
17971 …ER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */
17982 … /*!< Target Address Received during accepted IBI or Controller-role request */
18026 … I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */
18029 …DF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */
18097 … I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable…
18100 … I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt…
18156 …RF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */
18159 …F I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Fla…
18209 …R0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */
18236 … I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from…
18266 … I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */
18269 …GR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
18272 …C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C …
18349 …HOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */
18370 #define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-d…
18464 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
18470 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC …
18542 …IDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
18630 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet a…
18633 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet s…
18648 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet a…
18816 … WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to L…
18831 … WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
18921 … USB_ISTR_IDN_Msk /*!< EndPoint IDentifier (read-only bit) Mask */
18924 … USB_ISTR_DIR_Msk /*!< DIRection of transaction (read-only bit) Mask */
18930 … USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame (clear-only bit) Mask */
18933 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame (clear-…
18939 #define USB_ISTR_DCON USB_ISTR_DCON_Msk /*!< HOST MODE-Device Conne…
18942 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< SUSPend (clear-only bi…
18945 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< WaKe UP (clear-only bi…
18948 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< ERRor (clear-only bit)…
18951 …OVR USB_ISTR_PMAOVR_Msk /*!< PMA OVeR/underrun (clear-only bit) Mask */
18954 …R USB_ISTR_CTR_Msk /*!< Correct TRansfer (clear-only bit) Mask */
18977 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< status of D- data line…
19057 #define USB_BCDR_DPPU USB_BCDR_DPPU_Msk /*!< DP Pull-up Enable Mask…
19060 #define USB_BCDR_DPPD USB_BCDR_DPPD_Msk /*!< DP Pull-Down Enable Ma…
19284 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19285 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19288 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19291 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19292 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19293 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19294 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19295 #define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19296 #define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19297 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19298 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19299 #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19300 #define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19303 #define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19304 #define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19305 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19306 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19309 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19310 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19311 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19312 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19313 #define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19314 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19315 #define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19316 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19317 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19318 #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19321 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19322 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19323 #define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19326 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19327 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19328 #define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19329 #define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19330 #define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19331 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19332 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19333 #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19336 #define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19339 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19340 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19341 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19342 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19343 #define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19344 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19345 #define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19346 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19347 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19348 #define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19349 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19350 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19353 #define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19354 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19355 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19356 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
19357 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
19361 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19362 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19363 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19364 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19365 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19366 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19367 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19368 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19369 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19370 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19371 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19372 #define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19373 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19376 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19379 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19380 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19381 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19382 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19383 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19384 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19385 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19388 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19391 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19392 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19393 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19394 #define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19397 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19400 #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19401 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19402 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19405 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19408 #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19409 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19410 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19413 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19416 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19417 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19418 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19421 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19424 #define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19425 #define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19426 #define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19429 #define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19432 #define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19433 #define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19434 #define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19435 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19438 #define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19441 #define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19442 #define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19443 #define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19446 #define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19449 #define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19450 #define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19451 #define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19452 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19455 #define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19458 #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19459 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19460 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19461 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19464 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
19467 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19468 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19469 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
19470 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19473 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19476 #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19477 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19478 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19479 #define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19480 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19481 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19482 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19483 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19484 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19485 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19488 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19489 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19490 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19493 #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19494 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19495 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19496 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19497 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19498 #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19499 #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19500 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19501 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19502 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19503 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19504 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19505 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19508 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19509 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19510 #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19513 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19514 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19515 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19516 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19517 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19518 #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
19521 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19522 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19523 #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
19916 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
20095 /******************** UART Instances : Half-Duplex mode **********************/
20121 /******************** UART Instances : Wake-up from Stop mode **********************/