/** ****************************************************************************** * @file stm32h523xx.h * @author MCD Application Team * @brief CMSIS STM32H523xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #ifndef STM32H523xx_H #define STM32H523xx_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup ST * @{ */ /** @addtogroup STM32H523xx * @{ */ /** @addtogroup Configuration_of_CMSIS * @{ */ /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ /* =========================================================================================================================== */ typedef enum { /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ SecureFault_IRQn = -9, /*!< -9 Secure Fault */ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* =========================================== STM32H523xx Specific Interrupt Numbers ====================================== */ WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ RTC_IRQn = 2, /*!< RTC non-secure interrupt */ RTC_S_IRQn = 3, /*!< RTC secure interrupt */ TAMP_IRQn = 4, /*!< Tamper global interrupt */ RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ RCC_IRQn = 9, /*!< RCC non secure global interrupt */ RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ IWDG_IRQn = 35, /*!< IWDG global interrupt */ ADC1_IRQn = 37, /*!< ADC1 global interrupt */ DAC1_IRQn = 38, /*!< DAC1 global interrupt */ FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ TIM2_IRQn = 45, /*!< TIM2 global interrupt */ TIM3_IRQn = 46, /*!< TIM3 global interrupt */ TIM4_IRQn = 47, /*!< TIM4 global interrupt */ TIM5_IRQn = 48, /*!< TIM5 global interrupt */ TIM6_IRQn = 49, /*!< TIM6 global interrupt */ TIM7_IRQn = 50, /*!< TIM7 global interrupt */ I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ SPI1_IRQn = 55, /*!< SPI1 global interrupt */ SPI2_IRQn = 56, /*!< SPI2 global interrupt */ SPI3_IRQn = 57, /*!< SPI3 global interrupt */ USART1_IRQn = 58, /*!< USART1 global interrupt */ USART2_IRQn = 59, /*!< USART2 global interrupt */ USART3_IRQn = 60, /*!< USART3 global interrupt */ UART4_IRQn = 61, /*!< UART4 global interrupt */ UART5_IRQn = 62, /*!< UART5 global interrupt */ LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ ADC2_IRQn = 69, /*!< ADC2 global interrupt */ LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ TIM15_IRQn = 71, /*!< TIM15 global interrupt */ USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ CRS_IRQn = 75, /*!< CRS global interrupt */ UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ FMC_IRQn = 77, /*!< FMC global interrupt */ OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ SPI4_IRQn = 82, /*!< SPI4 global interrupt */ USART6_IRQn = 85, /*!< USART6 global interrupt */ GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ FPU_IRQn = 103, /*!< FPU global interrupt */ ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ DCMI_PSSI_IRQn = 108, /*!< DCMI/PSSI global interrupt */ FDCAN2_IT0_IRQn = 109, /*!< FDCAN2 interrupt 0 */ FDCAN2_IT1_IRQn = 110, /*!< FDCAN2 interrupt 1 */ DTS_IRQn = 113, /*!< DTS global interrupt */ RNG_IRQn = 114, /*!< RNG global interrupt */ HASH_IRQn = 117, /*!< HASH global interrupt */ PKA_IRQn = 118, /*!< PKA global interrupt */ CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ TIM12_IRQn = 120, /*!< TIM12 global interrupt */ I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ I3C2_EV_IRQn = 131, /*!< I3C2 Event interrupt */ I3C2_ER_IRQn = 132, /*!< I3C2 Error interrupt */ } IRQn_Type; /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ /* ------- Start of section using anonymous unions and disabling warnings ------- */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ #define __CM33_REV 0x0000U /* Core revision r0p1 */ #define __SAUREGION_PRESENT 1U /* SAU regions present */ #define __MPU_PRESENT 1U /* MPU present */ #define __VTOR_PRESENT 1U /* VTOR present */ #define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1U /* FPU present */ #define __DSP_PRESENT 1U /* DSP extension present */ /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32h5xx.h" /*!< STM32H5xx System */ /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32H5xx_peripherals * @{ */ /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ uint32_t RESERVED3[246]; /*!< Reserved, */ __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ } CRC_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; /** * @brief Improved Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ } I3C_TypeDef; /** * @brief DAC */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ __IO uint32_t RESERVED[1]; __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ } DAC_TypeDef; /** * @brief Clock Recovery System */ typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ } CRS_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ } HASH_TypeDef; /** * @brief HASH_DIGEST */ typedef struct { __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ } HASH_DIGEST_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ } RNG_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ } DBGMCU_TypeDef; /** * @brief DCMI */ typedef struct { __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; /** * @brief PSSI */ typedef struct { __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ } PSSI_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ } DMA_TypeDef; typedef struct { __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ } DMA_Channel_TypeDef; /** * @brief Asynch Interrupt/Event Controller (EXTI) */ typedef struct { __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ uint32_t RESERVED6[7]; /*!< Reserved6, Address offset: 0xA4-0xBF */ __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xC4-0xDC */ __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ uint32_t RESERVED9[7]; /*!< Reserved9, Address offset: 0x1A4-0x1BF */ __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ uint32_t RESERVED10[7]; /*!< Reserved10, Address offset: 0x1C4-0x1DC */ __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ } FLASH_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ } GPIO_TypeDef; /** * @brief Global TrustZone Controller */ typedef struct { __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ } GTZC_TZSC_TypeDef; typedef struct { __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ } GTZC_MPCBB_TypeDef; typedef struct { __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ } GTZC_TZIC_TypeDef; /** * @brief Instruction Cache */ typedef struct { __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ } ICACHE_TypeDef; /** * @brief Data Cache */ typedef struct { __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ } DCACHE_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ } LPTIM_TypeDef; /** * @brief OCTO Serial Peripheral Interface */ typedef struct { __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ } XSPI_TypeDef; typedef XSPI_TypeDef OCTOSPI_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ }PWR_TypeDef; /** * @brief SRAMs configuration controller */ typedef struct { __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ __IO uint32_t WPR3; /*!< SRAM Write Protection Register 3, Address offset: 0x20 */ __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ }RAMCFG_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ } RCC_TypeDef; /** * @brief PKA */ typedef struct { __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ } PKA_TypeDef; /* * @brief RTC Specific device feature definitions */ #define RTC_BKP_NB 32U #define RTC_TAMP_NB 8U /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ } RTC_TypeDef; /** * @brief Tamper and backup registers */ typedef struct { __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ } TAMP_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ } USART_TypeDef; /** * @brief System configuration, Boot and Security */ typedef struct { uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ } SBS_TypeDef; /** * @brief Secure digital input/output Interface */ typedef struct { __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ } SDMMC_TypeDef; /** * @brief Delay Block DLYB */ typedef struct { __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ } DLYB_TypeDef; /** * @brief UCPD */ typedef struct { __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ uint32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */ __IO uint32_t IPVER; /*!< UCPD IP version register, Address offset: 0x3F4 */ __IO uint32_t IPID; /*!< UCPD IP Identification register, Address offset: 0x3F8 */ __IO uint32_t MID; /*!< UCPD Magic Identification register, Address offset: 0x3FC */ } UCPD_TypeDef; /** * @brief Universal Serial Bus Full Speed Dual Role Device */ typedef struct { __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ __IO uint32_t RESERVED0[8]; /*!< Reserved, */ __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ __IO uint32_t RESERVED1; /*!< Reserved */ __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ } USB_DRD_TypeDef; /** * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table */ typedef struct { __IO uint32_t TXBD; /*!= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32H5xx_Peripheral_peripheralAddr * @{ */ /* Internal SRAMs size */ #define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ #define SRAM2_SIZE (0x14000UL) /*!< SRAM2=80k */ #define SRAM3_SIZE (0x10000UL) /*!< SRAM3=64k */ #define BKPSRAM_SIZE (0x00800UL) /*!< BKPSRAM=2k */ /* Flash, Peripheral and internal SRAMs base addresses - Non secure */ #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 512 KB) non-secure base address */ #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address */ #define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address */ #define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (64 KB) non-secure base address */ #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ /* External memories base addresses - Not aliased */ #define FMC_BASE (0x60000000UL) /*!< FMC base address */ #define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ #define FMC_BANK1 FMC_BASE #define FMC_BANK1_1 FMC_BANK1 #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) #define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ #define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ #define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ /* Peripheral memory map - Non secure */ #define APB1PERIPH_BASE_NS PERIPH_BASE_NS #define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) #define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) #define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) #define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) #define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) #define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) /*!< APB1 Non secure peripherals */ #define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) #define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) #define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) #define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) #define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) #define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) #define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) #define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) #define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) #define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) #define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) #define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) #define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) #define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) #define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) #define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) #define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) #define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) #define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) #define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) #define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) #define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) #define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) #define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) #define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) #define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) #define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) #define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) /*!< APB2 Non secure peripherals */ #define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) #define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) #define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) #define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) #define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) #define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) #define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) #define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) /*!< AHB1 Non secure peripherals */ #define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS #define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) #define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) #define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) #define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) #define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) #define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) #define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) #define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) #define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) #define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) #define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) #define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) #define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) #define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) #define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) #define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) #define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) #define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) #define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) #define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) #define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) #define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) #define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) #define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) #define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) #define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) #define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) #define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) #define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) #define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) #define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) #define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) /*!< AHB2 Non secure peripherals */ #define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) #define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) #define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) #define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) #define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) #define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) #define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) #define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) #define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) #define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) #define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) #define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) #define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) #define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) #define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) #define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) #define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) #define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) #define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) /*!< APB3 Non secure peripherals */ #define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) #define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) #define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) #define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) #define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) #define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) #define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) #define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) /*!< AHB3 Non secure peripherals */ #define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) #define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) #define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) #define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) /*!< AHB4 Non secure peripherals */ #define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) #define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) #define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ #define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ #define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) /*!< FMC Banks Non secure registers base address */ #define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) #define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) #define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) /* Flash, Peripheral and internal SRAMs base addresses - Secure */ #define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 512 KB) secure base address */ #define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (128 KB) secure base address */ #define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ #define SRAM3_BASE_S (0x30034000UL) /*!< SRAM3 (64 KB) secure base address */ #define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ /* Peripheral memory map - Secure */ #define APB1PERIPH_BASE_S PERIPH_BASE_S #define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) #define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) #define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) #define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) #define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) #define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) /*!< APB1 secure peripherals */ #define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) #define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) #define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) #define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) #define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) #define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) #define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) #define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) #define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) #define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) #define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) #define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) #define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) #define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) #define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) #define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) #define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) #define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) #define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) #define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) #define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) #define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) #define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) #define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) #define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) #define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) #define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) #define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) /*!< APB2 Secure peripherals */ #define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) #define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) #define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) #define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) #define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) #define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) #define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) #define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) /*!< AHB1 secure peripherals */ #define GPDMA1_BASE_S AHB1PERIPH_BASE_S #define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) #define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) #define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) #define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) #define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) #define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) #define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) #define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) #define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) #define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) #define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) #define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) #define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) #define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) #define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) #define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) #define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) #define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) #define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) #define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) #define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) #define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) #define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) #define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) #define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) #define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) #define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) #define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) #define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) #define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) #define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) #define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) /*!< AHB2 secure peripherals */ #define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) #define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) #define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) #define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) #define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) #define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) #define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) #define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) #define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) #define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) #define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) #define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) #define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) #define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) #define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) #define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) #define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) #define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) #define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) /*!< APB3 secure peripherals */ #define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) #define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) #define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) #define I3C2_BASE_S (APB3PERIPH_BASE_S + 0x3000UL) #define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) #define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) #define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) #define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) /*!< AHB3 secure peripherals */ #define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) #define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) #define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) #define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) /*!< AHB4 secure peripherals */ #define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) #define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) #define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ #define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ #define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) /*!< FMC Banks Non secure registers base address */ #define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) #define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) #define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) /* Debug MCU registers base address */ #define DBGMCU_BASE (0x44024000UL) #define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ #define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ /* Internal Flash OTP Area */ #define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ #define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ /* Flash system Area */ #define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ #define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ #define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ /* Internal Flash EDATA Area */ #define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ #define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ #define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ /* Internal Flash OBK Area */ #define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ #define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ #define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ #define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ #define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ #define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ #define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ #define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ #define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ #define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ #define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ #define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ #define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ #define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ #define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ #define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ #define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ #define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ #endif /* CMSE */ /*!< Root Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) #define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) /************ RSSLIB function return constants ********************************/ #define RSSLIB_ERROR (0xF5F5F5F5UL) #define RSSLIB_SUCCESS (0xEAEAEAEAUL) /*!< RSSLIB pointer function structure address definition */ #define RSSLIB_PFUNC_BASE (0xBF9FB68UL) #define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) /** * @brief Prototype of RSSLIB Jump to HDP level2 Function * @detail This function increments HDP level up to HDP level 2 * Then it enables the MPU region corresponding the MPU index * provided as input parameter. The Vector Table shall be located * within this MPU region. * Then it jumps to the reset handler present within the * Vector table. The function does not return on successful execution. * @param pointer on the vector table containing the reset handler the function * jumps to. * @param MPU region index containing the vector table * jumps to. * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); /** * @brief Prototype of RSSLIB Jump to HDP level3 Function * @detail This function increments HDP level up to HDP level 3 * Then it enables the MPU region corresponding the MPU index * provided as input parameter. The Vector Table shall be located * within this MPU region. * Then it jumps to the reset handler present within the * Vector table. The function does not return on successful execution. * @param pointer on the vector table containing the reset handler the function * jumps to. * @param MPU region index containing the vector table * jumps to. * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); /** * @brief Prototype of RSSLIB Jump to HDP level3 Function * @detail This function increments HDP level up to HDP level 3 * Then it jumps to the non-secure reset handler present within the * Vector table. The function does not return on successful execution. * @param pointer on the vector table containing the reset handler the function * jumps to. * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); /** * @brief Input parameter definition of RSSLIB_DataProvisioning */ typedef struct { uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ } RSSLIB_DataProvisioningConf_t; /** * @brief Prototype of RSSLIB Data Provisioning Function * @detail This function write Data within OBKeys sections. * @param pointer on the structure defining Data to be provisioned and where to * provision them within OBKeys sections. * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); /** * @brief RSSLib secure callable function pointer structure */ typedef struct { __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; } S_pFuncTypeDef; /** * @brief RSSLib Non-secure callable function pointer structure */ typedef struct { __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; } NSC_pFuncTypeDef; /** * @brief RSSLib function pointer structure */ typedef struct { NSC_pFuncTypeDef NSC; uint32_t RESERVED1[3]; S_pFuncTypeDef S; }RSSLIB_pFunc_TypeDef; /*!< Non Secure Service Library */ /************ RSSLIB SAU system Flash region definition constants *************/ #define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) #define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) /************ RSSLIB function return constants ********************************/ #define NSSLIB_ERROR (0xF5F5F5F5UL) #define NSSLIB_SUCCESS (0xEAEAEAEAUL) /*!< RSSLIB pointer function structure address definition */ #define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) #define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) /** * @brief Prototype of RSSLIB Jump to HDP level2 Function * @detail This function increments HDP level up to HDP level 2 * Then it enables the MPU region corresponding the MPU index * provided as input parameter. The Vector Table shall be located * within this MPU region. * Then it jumps to the reset handler present within the * Vector table. The function does not return on successful execution. * @param pointer on the vector table containing the reset handler the function * jumps to. * @param MPU region index containing the vector table * jumps to. * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); /** * @brief Prototype of RSSLIB Jump to HDP level3 Function * @detail This function increments HDP level up to HDP level 3 * Then it enables the MPU region corresponding the MPU index * provided as input parameter. The Vector Table shall be located * within this MPU region. * Then it jumps to the reset handler present within the * Vector table. The function does not return on successful execution. * @param pointer on the vector table containing the reset handler the function * jumps to. * @param MPU region index containing the vector table * jumps to. * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. */ typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); /** * @brief RSSLib secure callable function pointer structure */ typedef struct { __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; } NSSLIB_pFunc_TypeDef; /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /** @addtogroup STM32H5xx_Peripheral_declaration * @{ */ /*!< APB1 Non secure peripherals */ #define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) #define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) #define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) #define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) #define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) #define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) #define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) #define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) #define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) #define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) #define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) #define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) #define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) #define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) #define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) #define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) #define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) #define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) #define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) #define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) #define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) #define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) #define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) #define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) #define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) #define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) #define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) #define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) #define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) /*!< APB2 Non secure peripherals */ #define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) #define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) #define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) #define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) #define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) #define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) #define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) #define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) /*!< AHB1 Non secure peripherals */ #define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) #define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) #define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) #define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) #define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) #define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) #define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) #define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) #define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) #define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) #define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) #define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) #define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) #define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) #define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) #define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) #define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) #define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) #define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) #define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) #define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) #define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) #define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) #define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) #define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) #define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) #define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) #define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) #define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) #define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) #define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) /*!< AHB2 Non secure peripherals */ #define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) #define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) #define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) #define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) #define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) #define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) #define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) #define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) #define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) #define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) #define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) #define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) #define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) #define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) #define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) #define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) #define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) #define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) /*!< APB3 Non secure peripherals */ #define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) #define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) #define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) #define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) #define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) #define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) #define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) #define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) /*!< AHB3 Non secure peripherals */ #define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) #define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) #define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) /*!< AHB4 Non secure peripherals */ #define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) #define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) #define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) #define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) /*!< FMC Banks Non secure registers base address */ #define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) #define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) #define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) /*!< APB1 Secure peripherals */ #define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) #define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) #define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) #define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) #define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) #define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) #define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) #define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) #define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) #define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) #define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) #define USART2_S ((USART_TypeDef *)USART2_BASE_S) #define USART3_S ((USART_TypeDef *)USART3_BASE_S) #define UART4_S ((USART_TypeDef *)UART4_BASE_S) #define UART5_S ((USART_TypeDef *)UART5_BASE_S) #define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) #define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) #define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) #define CRS_S ((CRS_TypeDef *)CRS_BASE_S) #define USART6_S ((USART_TypeDef *)USART6_BASE_S) #define CEC_S ((CEC_TypeDef *)CEC_BASE_S) #define DTS_S ((DTS_TypeDef *)DTS_BASE_S) #define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) #define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) #define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) #define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) #define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) /*!< APB2 secure peripherals */ #define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) #define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) #define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) #define USART1_S ((USART_TypeDef *) USART1_BASE_S) #define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) #define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) #define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) #define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) /*!< AHB1 secure peripherals */ #define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) #define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) #define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) #define CRC_S ((CRC_TypeDef *) CRC_BASE_S) #define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) #define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) #define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) #define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) #define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) #define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) #define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) #define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) #define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) #define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) #define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) #define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) #define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) #define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) #define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) #define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) #define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) #define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) #define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) #define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) #define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) #define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) #define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) #define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) #define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) #define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) #define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) /*!< AHB2 secure peripherals */ #define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) #define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) #define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) #define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) #define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) #define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) #define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) #define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) #define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) #define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) #define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) #define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) #define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) #define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) #define HASH_S ((HASH_TypeDef *) HASH_BASE_S) #define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) #define RNG_S ((RNG_TypeDef *) RNG_BASE_S) #define PKA_S ((PKA_TypeDef *) PKA_BASE_S) /*!< APB3 secure peripherals */ #define SBS_S ((SBS_TypeDef *) SBS_BASE_S) #define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) #define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) #define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) #define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) #define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) #define RTC_S ((RTC_TypeDef *) RTC_BASE_S) #define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) /*!< AHB3 Secure peripherals */ #define PWR_S ((PWR_TypeDef *) PWR_BASE_S) #define RCC_S ((RCC_TypeDef *) RCC_BASE_S) #define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) /*!< AHB4 secure peripherals */ #define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) #define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) #define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) #define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) #define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) #define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) #define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /*!< Memory base addresses for Secure peripherals */ #define FLASH_BASE FLASH_BASE_S #define FLASH_OBK_BASE FLASH_OBK_BASE_S #define FLASH_EDATA_BASE FLASH_EDATA_BASE_S #define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S #define SRAM1_BASE SRAM1_BASE_S #define SRAM2_BASE SRAM2_BASE_S #define SRAM3_BASE SRAM3_BASE_S #define BKPSRAM_BASE BKPSRAM_BASE_S #define PERIPH_BASE PERIPH_BASE_S #define APB1PERIPH_BASE APB1PERIPH_BASE_S #define APB2PERIPH_BASE APB2PERIPH_BASE_S #define APB3PERIPH_BASE APB3PERIPH_BASE_S #define AHB1PERIPH_BASE AHB1PERIPH_BASE_S #define AHB2PERIPH_BASE AHB2PERIPH_BASE_S #define AHB3PERIPH_BASE AHB3PERIPH_BASE_S #define AHB4PERIPH_BASE AHB4PERIPH_BASE_S /*!< Instance aliases and base addresses for Secure peripherals */ #define RCC RCC_S #define RCC_BASE RCC_BASE_S #define DCMI DCMI_S #define DCMI_BASE DCMI_BASE_S #define PSSI PSSI_S #define PSSI_BASE PSSI_BASE_S #define DTS DTS_S #define DTS_BASE DTS_BASE_S #define FLASH FLASH_S #define FLASH_R_BASE FLASH_R_BASE_S #define GPDMA1 GPDMA1_S #define GPDMA1_BASE GPDMA1_BASE_S #define GPDMA1_Channel0 GPDMA1_Channel0_S #define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S #define GPDMA1_Channel1 GPDMA1_Channel1_S #define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S #define GPDMA1_Channel2 GPDMA1_Channel2_S #define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S #define GPDMA1_Channel3 GPDMA1_Channel3_S #define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S #define GPDMA1_Channel4 GPDMA1_Channel4_S #define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S #define GPDMA1_Channel5 GPDMA1_Channel5_S #define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S #define GPDMA1_Channel6 GPDMA1_Channel6_S #define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S #define GPDMA1_Channel7 GPDMA1_Channel7_S #define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S #define GPDMA2 GPDMA2_S #define GPDMA2_BASE GPDMA2_BASE_S #define GPDMA2_Channel0 GPDMA2_Channel0_S #define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S #define GPDMA2_Channel1 GPDMA2_Channel1_S #define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S #define GPDMA2_Channel2 GPDMA2_Channel2_S #define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S #define GPDMA2_Channel3 GPDMA2_Channel3_S #define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S #define GPDMA2_Channel4 GPDMA2_Channel4_S #define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S #define GPDMA2_Channel5 GPDMA2_Channel5_S #define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S #define GPDMA2_Channel6 GPDMA2_Channel6_S #define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S #define GPDMA2_Channel7 GPDMA2_Channel7_S #define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S #define GPIOA GPIOA_S #define GPIOA_BASE GPIOA_BASE_S #define GPIOB GPIOB_S #define GPIOB_BASE GPIOB_BASE_S #define GPIOC GPIOC_S #define GPIOC_BASE GPIOC_BASE_S #define GPIOD GPIOD_S #define GPIOD_BASE GPIOD_BASE_S #define GPIOE GPIOE_S #define GPIOE_BASE GPIOE_BASE_S #define GPIOF GPIOF_S #define GPIOF_BASE GPIOF_BASE_S #define GPIOG GPIOG_S #define GPIOG_BASE GPIOG_BASE_S #define GPIOH GPIOH_S #define GPIOH_BASE GPIOH_BASE_S #define PWR PWR_S #define PWR_BASE PWR_BASE_S #define RAMCFG_SRAM1 RAMCFG_SRAM1_S #define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S #define RAMCFG_SRAM2 RAMCFG_SRAM2_S #define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S #define RAMCFG_SRAM3 RAMCFG_SRAM3_S #define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S #define RAMCFG_BKPRAM RAMCFG_BKPRAM_S #define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S #define EXTI EXTI_S #define EXTI_BASE EXTI_BASE_S #define ICACHE ICACHE_S #define ICACHE_BASE ICACHE_BASE_S #define DCACHE1 DCACHE1_S #define DCACHE1_BASE DCACHE1_BASE_S #define GTZC_TZSC1 GTZC_TZSC1_S #define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S #define GTZC_TZIC1 GTZC_TZIC1_S #define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S #define GTZC_MPCBB1 GTZC_MPCBB1_S #define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S #define GTZC_MPCBB2 GTZC_MPCBB2_S #define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S #define GTZC_MPCBB3 GTZC_MPCBB3_S #define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S #define RTC RTC_S #define RTC_BASE RTC_BASE_S #define TAMP TAMP_S #define TAMP_BASE TAMP_BASE_S #define TIM1 TIM1_S #define TIM1_BASE TIM1_BASE_S #define TIM2 TIM2_S #define TIM2_BASE TIM2_BASE_S #define TIM3 TIM3_S #define TIM3_BASE TIM3_BASE_S #define TIM4 TIM4_S #define TIM4_BASE TIM4_BASE_S #define TIM5 TIM5_S #define TIM5_BASE TIM5_BASE_S #define TIM6 TIM6_S #define TIM6_BASE TIM6_BASE_S #define TIM7 TIM7_S #define TIM7_BASE TIM7_BASE_S #define TIM8 TIM8_S #define TIM8_BASE TIM8_BASE_S #define TIM15 TIM15_S #define TIM15_BASE TIM15_BASE_S #define TIM12 TIM12_S #define TIM12_BASE TIM12_BASE_S #define WWDG WWDG_S #define WWDG_BASE WWDG_BASE_S #define IWDG IWDG_S #define IWDG_BASE IWDG_BASE_S #define SPI1 SPI1_S #define SPI1_BASE SPI1_BASE_S #define SPI2 SPI2_S #define SPI2_BASE SPI2_BASE_S #define SPI3 SPI3_S #define SPI3_BASE SPI3_BASE_S #define SPI4 SPI4_S #define SPI4_BASE SPI4_BASE_S #define USART1 USART1_S #define USART1_BASE USART1_BASE_S #define USART2 USART2_S #define USART2_BASE USART2_BASE_S #define USART3 USART3_S #define USART3_BASE USART3_BASE_S #define UART4 UART4_S #define UART4_BASE UART4_BASE_S #define UART5 UART5_S #define UART5_BASE UART5_BASE_S #define USART6 USART6_S #define USART6_BASE USART6_BASE_S #define CEC CEC_S #define CEC_BASE CEC_BASE_S #define I2C1 I2C1_S #define I2C1_BASE I2C1_BASE_S #define I2C2 I2C2_S #define I2C2_BASE I2C2_BASE_S #define I2C3 I2C3_S #define I2C3_BASE I2C3_BASE_S #define I3C1 I3C1_S #define I3C1_BASE I3C1_BASE_S #define I3C2 I3C2_S #define I3C2_BASE I3C2_BASE_S #define CRS CRS_S #define CRS_BASE CRS_BASE_S #define FDCAN1 FDCAN1_S #define FDCAN1_BASE FDCAN1_BASE_S #define FDCAN_CONFIG FDCAN_CONFIG_S #define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S #define SRAMCAN_BASE SRAMCAN_BASE_S #define FDCAN2 FDCAN2_S #define FDCAN2_BASE FDCAN2_BASE_S #define DAC1 DAC1_S #define DAC1_BASE DAC1_BASE_S #define LPTIM1 LPTIM1_S #define LPTIM1_BASE LPTIM1_BASE_S #define LPTIM2 LPTIM2_S #define LPTIM2_BASE LPTIM2_BASE_S #define LPUART1 LPUART1_S #define LPUART1_BASE LPUART1_BASE_S #define UCPD1 UCPD1_S #define UCPD1_BASE UCPD1_BASE_S #define SBS SBS_S #define SBS_BASE SBS_BASE_S #define VREFBUF VREFBUF_S #define VREFBUF_BASE VREFBUF_BASE_S #define USB_DRD_FS USB_DRD_FS_S #define USB_DRD_BASE USB_DRD_BASE_S #define USB_DRD_PMAADDR USB_DRD_PMAADDR_S #define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S #define CRC CRC_S #define CRC_BASE CRC_BASE_S #define ADC1 ADC1_S #define ADC1_BASE ADC1_BASE_S #define ADC2 ADC2_S #define ADC2_BASE ADC2_BASE_S #define ADC12_COMMON ADC12_COMMON_S #define ADC12_COMMON_BASE ADC12_COMMON_BASE_S #define HASH HASH_S #define HASH_BASE HASH_BASE_S #define HASH_DIGEST HASH_DIGEST_S #define HASH_DIGEST_BASE HASH_DIGEST_BASE_S #define RNG RNG_S #define RNG_BASE RNG_BASE_S #define PKA PKA_S #define PKA_BASE PKA_BASE_S #define PKA_RAM_BASE PKA_RAM_BASE_S #define SDMMC1 SDMMC1_S #define SDMMC1_BASE SDMMC1_BASE_S #define FMC_Bank1_R FMC_Bank1_R_S #define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S #define FMC_Bank1E_R FMC_Bank1E_R_S #define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S #define FMC_Bank3_R FMC_Bank3_R_S #define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S #define OCTOSPI1 OCTOSPI1_S #define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S #define DLYB_SDMMC1 DLYB_SDMMC1_S #define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S #define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S #define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S #else /*!< Memory base addresses for Non secure peripherals */ #define FLASH_BASE FLASH_BASE_NS #define FLASH_OBK_BASE FLASH_OBK_BASE_NS #define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS #define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS #define SRAM1_BASE SRAM1_BASE_NS #define SRAM2_BASE SRAM2_BASE_NS #define SRAM3_BASE SRAM3_BASE_NS #define BKPSRAM_BASE BKPSRAM_BASE_NS #define PERIPH_BASE PERIPH_BASE_NS #define APB1PERIPH_BASE APB1PERIPH_BASE_NS #define APB2PERIPH_BASE APB2PERIPH_BASE_NS #define APB3PERIPH_BASE APB3PERIPH_BASE_NS #define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS #define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS #define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS #define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS /*!< Instance aliases and base addresses for Non secure peripherals */ #define RCC RCC_NS #define RCC_BASE RCC_BASE_NS #define DCMI DCMI_NS #define DCMI_BASE DCMI_BASE_NS #define PSSI PSSI_NS #define PSSI_BASE PSSI_BASE_NS #define DTS DTS_NS #define DTS_BASE DTS_BASE_NS #define FLASH FLASH_NS #define FLASH_R_BASE FLASH_R_BASE_NS #define GPDMA1 GPDMA1_NS #define GPDMA1_BASE GPDMA1_BASE_NS #define GPDMA1_Channel0 GPDMA1_Channel0_NS #define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS #define GPDMA1_Channel1 GPDMA1_Channel1_NS #define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS #define GPDMA1_Channel2 GPDMA1_Channel2_NS #define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS #define GPDMA1_Channel3 GPDMA1_Channel3_NS #define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS #define GPDMA1_Channel4 GPDMA1_Channel4_NS #define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS #define GPDMA1_Channel5 GPDMA1_Channel5_NS #define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS #define GPDMA1_Channel6 GPDMA1_Channel6_NS #define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS #define GPDMA1_Channel7 GPDMA1_Channel7_NS #define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS #define GPDMA2 GPDMA2_NS #define GPDMA2_BASE GPDMA2_BASE_NS #define GPDMA2_Channel0 GPDMA2_Channel0_NS #define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS #define GPDMA2_Channel1 GPDMA2_Channel1_NS #define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS #define GPDMA2_Channel2 GPDMA2_Channel2_NS #define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS #define GPDMA2_Channel3 GPDMA2_Channel3_NS #define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS #define GPDMA2_Channel4 GPDMA2_Channel4_NS #define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS #define GPDMA2_Channel5 GPDMA2_Channel5_NS #define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS #define GPDMA2_Channel6 GPDMA2_Channel6_NS #define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS #define GPDMA2_Channel7 GPDMA2_Channel7_NS #define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS #define GPIOA GPIOA_NS #define GPIOA_BASE GPIOA_BASE_NS #define GPIOB GPIOB_NS #define GPIOB_BASE GPIOB_BASE_NS #define GPIOC GPIOC_NS #define GPIOC_BASE GPIOC_BASE_NS #define GPIOD GPIOD_NS #define GPIOD_BASE GPIOD_BASE_NS #define GPIOE GPIOE_NS #define GPIOE_BASE GPIOE_BASE_NS #define GPIOF GPIOF_NS #define GPIOF_BASE GPIOF_BASE_NS #define GPIOG GPIOG_NS #define GPIOG_BASE GPIOG_BASE_NS #define GPIOH GPIOH_NS #define GPIOH_BASE GPIOH_BASE_NS #define PWR PWR_NS #define PWR_BASE PWR_BASE_NS #define RAMCFG_SRAM1 RAMCFG_SRAM1_NS #define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS #define RAMCFG_SRAM2 RAMCFG_SRAM2_NS #define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS #define RAMCFG_SRAM3 RAMCFG_SRAM3_NS #define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS #define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS #define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS #define EXTI EXTI_NS #define EXTI_BASE EXTI_BASE_NS #define ICACHE ICACHE_NS #define ICACHE_BASE ICACHE_BASE_NS #define DCACHE1 DCACHE1_NS #define DCACHE1_BASE DCACHE1_BASE_NS #define GTZC_TZSC1 GTZC_TZSC1_NS #define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS #define GTZC_TZIC1 GTZC_TZIC1_NS #define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS #define GTZC_MPCBB1 GTZC_MPCBB1_NS #define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS #define GTZC_MPCBB2 GTZC_MPCBB2_NS #define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS #define GTZC_MPCBB3 GTZC_MPCBB3_NS #define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS #define RTC RTC_NS #define RTC_BASE RTC_BASE_NS #define TAMP TAMP_NS #define TAMP_BASE TAMP_BASE_NS #define TIM1 TIM1_NS #define TIM1_BASE TIM1_BASE_NS #define TIM2 TIM2_NS #define TIM2_BASE TIM2_BASE_NS #define TIM3 TIM3_NS #define TIM3_BASE TIM3_BASE_NS #define TIM4 TIM4_NS #define TIM4_BASE TIM4_BASE_NS #define TIM5 TIM5_NS #define TIM5_BASE TIM5_BASE_NS #define TIM6 TIM6_NS #define TIM6_BASE TIM6_BASE_NS #define TIM7 TIM7_NS #define TIM7_BASE TIM7_BASE_NS #define TIM8 TIM8_NS #define TIM8_BASE TIM8_BASE_NS #define TIM12 TIM12_NS #define TIM12_BASE TIM12_BASE_NS #define TIM15 TIM15_NS #define TIM15_BASE TIM15_BASE_NS #define WWDG WWDG_NS #define WWDG_BASE WWDG_BASE_NS #define IWDG IWDG_NS #define IWDG_BASE IWDG_BASE_NS #define SPI1 SPI1_NS #define SPI1_BASE SPI1_BASE_NS #define SPI2 SPI2_NS #define SPI2_BASE SPI2_BASE_NS #define SPI3 SPI3_NS #define SPI3_BASE SPI3_BASE_NS #define SPI4 SPI4_NS #define SPI4_BASE SPI4_BASE_NS #define USART1 USART1_NS #define USART1_BASE USART1_BASE_NS #define USART2 USART2_NS #define USART2_BASE USART2_BASE_NS #define USART3 USART3_NS #define USART3_BASE USART3_BASE_NS #define UART4 UART4_NS #define UART4_BASE UART4_BASE_NS #define UART5 UART5_NS #define UART5_BASE UART5_BASE_NS #define USART6 USART6_NS #define USART6_BASE USART6_BASE_NS #define CEC CEC_NS #define CEC_BASE CEC_BASE_NS #define I2C1 I2C1_NS #define I2C1_BASE I2C1_BASE_NS #define I2C2 I2C2_NS #define I2C2_BASE I2C2_BASE_NS #define I2C3 I2C3_NS #define I2C3_BASE I2C3_BASE_NS #define I3C1 I3C1_NS #define I3C1_BASE I3C1_BASE_NS #define I3C2 I3C2_NS #define I3C2_BASE I3C2_BASE_NS #define CRS CRS_NS #define CRS_BASE CRS_BASE_NS #define FDCAN1 FDCAN1_NS #define FDCAN1_BASE FDCAN1_BASE_NS #define FDCAN_CONFIG FDCAN_CONFIG_NS #define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS #define SRAMCAN_BASE SRAMCAN_BASE_NS #define FDCAN2 FDCAN2_NS #define FDCAN2_BASE FDCAN2_BASE_NS #define DAC1 DAC1_NS #define DAC1_BASE DAC1_BASE_NS #define LPTIM1 LPTIM1_NS #define LPTIM1_BASE LPTIM1_BASE_NS #define LPTIM2 LPTIM2_NS #define LPTIM2_BASE LPTIM2_BASE_NS #define LPUART1 LPUART1_NS #define LPUART1_BASE LPUART1_BASE_NS #define UCPD1 UCPD1_NS #define UCPD1_BASE UCPD1_BASE_NS #define SBS SBS_NS #define SBS_BASE SBS_BASE_NS #define VREFBUF VREFBUF_NS #define VREFBUF_BASE VREFBUF_BASE_NS #define USB_DRD_FS USB_DRD_FS_NS #define USB_DRD_BASE USB_DRD_BASE_NS #define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS #define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS #define CRC CRC_NS #define CRC_BASE CRC_BASE_NS #define ADC1 ADC1_NS #define ADC1_BASE ADC1_BASE_NS #define ADC2 ADC2_NS #define ADC2_BASE ADC2_BASE_NS #define ADC12_COMMON ADC12_COMMON_NS #define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS #define HASH HASH_NS #define HASH_BASE HASH_BASE_NS #define HASH_DIGEST HASH_DIGEST_NS #define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS #define RNG RNG_NS #define RNG_BASE RNG_BASE_NS #define PKA PKA_NS #define PKA_BASE PKA_BASE_NS #define PKA_RAM_BASE PKA_RAM_BASE_NS #define SDMMC1 SDMMC1_NS #define SDMMC1_BASE SDMMC1_BASE_NS #define FMC_Bank1_R FMC_Bank1_R_NS #define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS #define FMC_Bank1E_R FMC_Bank1E_R_NS #define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS #define FMC_Bank3_R FMC_Bank3_R_NS #define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS #define OCTOSPI1 OCTOSPI1_NS #define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS #define DLYB_SDMMC1 DLYB_SDMMC1_NS #define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS #define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS #define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS #endif /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_EXTSEL_Pos (5U) #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ #define ADC_CFGR2_GCOMP_Pos (16U) #define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ #define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ #define ADC_CFGR2_SWTRIG_Pos (25U) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ #define ADC_CFGR2_BULB_Pos (26U) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ #define ADC_CFGR2_SMPTRIG_Pos (27U) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ #define ADC_CFGR2_LFTRIG_Pos (29U) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ #define ADC_SMPR1_SMPPLUS_Pos (31U) #define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR1_AWDFILT_Pos (12U) #define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ #define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ #define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ #define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ #define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ #define ADC_TR1_HT1_Pos (16U) #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_TR2_HT2_Pos (16U) #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_TR3_HT3_Pos (16U) #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_Pos (7U) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ1_Pos (9U) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ2_Pos (15U) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (21U) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ #define ADC_JSQR_JSQ4_Pos (27U) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ #define ADC_OFR1_OFFSETPOS_Pos (24U) #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR1_SATEN_Pos (25U) #define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ #define ADC_OFR2_OFFSETPOS_Pos (24U) #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ #define ADC_OFR2_SATEN_Pos (25U) #define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ #define ADC_OFR3_OFFSETPOS_Pos (24U) #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ #define ADC_OFR3_SATEN_Pos (25U) #define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ #define ADC_OFR4_OFFSETPOS_Pos (24U) #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ #define ADC_OFR4_SATEN_Pos (25U) #define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ /******************** Bit definition for ADC_OR register *****************/ #define ADC_OR_OP0_Pos (0U) #define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ #define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ #define ADC_OR_OP1_Pos (1U) #define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ #define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATEN_Pos (24U) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ #define ADC_CDR_RDATA_SLV_Pos (16U) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /******************************************************************************/ /* */ /* CRC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ #define CRC_CR_POLYSIZE_Pos (3U) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ #define CRC_CR_REV_IN_Pos (5U) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ #define CRC_CR_REV_OUT_Pos (7U) #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT_Pos (0U) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ #define CRC_POL_POL_Pos (0U) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ #define CRS_CR_SYNCOKIE_Pos (0U) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ #define CRS_CR_SYNCWARNIE_Pos (1U) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ #define CRS_CR_ERRIE_Pos (2U) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ #define CRS_CR_ESYNCIE_Pos (3U) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ #define CRS_CR_CEN_Pos (5U) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ #define CRS_CR_AUTOTRIMEN_Pos (6U) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ #define CRS_CR_SWSYNC_Pos (7U) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ #define CRS_CFGR_RELOAD_Pos (0U) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ #define CRS_CFGR_FELIM_Pos (16U) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ #define CRS_CFGR_SYNCDIV_Pos (24U) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ #define CRS_CFGR_SYNCSRC_Pos (28U) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ #define CRS_CFGR_SYNCPOL_Pos (31U) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ #define CRS_ISR_SYNCOKF_Pos (0U) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ #define CRS_ISR_SYNCWARNF_Pos (1U) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ #define CRS_ISR_ERRF_Pos (2U) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ #define CRS_ISR_ESYNCF_Pos (3U) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ #define CRS_ISR_SYNCERR_Pos (8U) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ #define CRS_ISR_SYNCMISS_Pos (9U) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ #define CRS_ISR_TRIMOVF_Pos (10U) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ #define CRS_ISR_FEDIR_Pos (15U) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ #define CRS_ISR_FECAP_Pos (16U) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ #define CRS_ICR_SYNCOKC_Pos (0U) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ #define CRS_ICR_SYNCWARNC_Pos (1U) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ #define CRS_ICR_ERRC_Pos (2U) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ #define CRS_ICR_ESYNCC_Pos (3U) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ /******************************************************************************/ /* */ /* RNG */ /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk #define RNG_CR_IE_Pos (3U) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ #define RNG_CR_IE RNG_CR_IE_Msk #define RNG_CR_CED_Pos (5U) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ #define RNG_CR_CED RNG_CR_CED_Msk #define RNG_CR_ARDIS_Pos (7U) #define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) #define RNG_CR_ARDIS RNG_CR_ARDIS_Msk #define RNG_CR_RNG_CONFIG3_Pos (8U) #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk #define RNG_CR_NISTC_Pos (12U) #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) #define RNG_CR_NISTC RNG_CR_NISTC_Msk #define RNG_CR_RNG_CONFIG2_Pos (13U) #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk #define RNG_CR_CONDRST_Pos (30U) #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk #define RNG_CR_CONFIGLOCK_Pos (31U) #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ #define RNG_SR_DRDY RNG_SR_DRDY_Msk #define RNG_SR_CECS_Pos (1U) #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ #define RNG_SR_CECS RNG_SR_CECS_Msk #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk #define RNG_SR_SEIS_Pos (6U) #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************** Bits definition for RNG_HTCR register *******************/ #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values ******************************/ #define RNG_CR_NIST_VALUE (0x00F00D00U) #define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ /* */ /* Digital to Analog Converter */ /* */ /******************************************************************************/ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ #define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ /******************* Bits definition for FLASH_ACR register *****************/ #define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000U) #define FLASH_ACR_LATENCY_1WS (0x00000001U) #define FLASH_ACR_LATENCY_2WS (0x00000002U) #define FLASH_ACR_LATENCY_3WS (0x00000003U) #define FLASH_ACR_LATENCY_4WS (0x00000004U) #define FLASH_ACR_LATENCY_5WS (0x00000005U) #define FLASH_ACR_LATENCY_6WS (0x00000006U) #define FLASH_ACR_LATENCY_7WS (0x00000007U) #define FLASH_ACR_LATENCY_8WS (0x00000008U) #define FLASH_ACR_LATENCY_9WS (0x00000009U) #define FLASH_ACR_LATENCY_10WS (0x0000000AU) #define FLASH_ACR_LATENCY_11WS (0x0000000BU) #define FLASH_ACR_LATENCY_12WS (0x0000000CU) #define FLASH_ACR_LATENCY_13WS (0x0000000DU) #define FLASH_ACR_LATENCY_14WS (0x0000000EU) #define FLASH_ACR_LATENCY_15WS (0x0000000FU) #define FLASH_ACR_WRHIGHFREQ_Pos (4U) #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ #define FLASH_ACR_PRFTEN_Pos (8U) #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ /******************* Bits definition for FLASH_OPSR register ***************/ #define FLASH_OPSR_ADDR_OP_Pos (0U) #define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ #define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ #define FLASH_OPSR_DATA_OP_Pos (21U) #define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ #define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ #define FLASH_OPSR_BK_OP_Pos (22U) #define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ #define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ #define FLASH_OPSR_SYSF_OP_Pos (23U) #define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ #define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ #define FLASH_OPSR_OTP_OP_Pos (24U) #define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ #define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ #define FLASH_OPSR_CODE_OP_Pos (29U) #define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ #define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ #define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ #define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ #define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ /******************* Bits definition for FLASH_OPTCR register *******************/ #define FLASH_OPTCR_OPTLOCK_Pos (0U) #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ #define FLASH_OPTCR_OPTSTART_Pos (1U) #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ #define FLASH_OPTCR_SWAP_BANK_Pos (31U) #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ #define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ /******************* Bits definition for FLASH_SR register ***********************/ #define FLASH_SR_BSY_Pos (0U) #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ #define FLASH_SR_WBNE_Pos (1U) #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ #define FLASH_SR_DBNE_Pos (3U) #define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ #define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ #define FLASH_SR_EOP_Pos (16U) #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ #define FLASH_SR_WRPERR_Pos (17U) #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ #define FLASH_SR_PGSERR_Pos (18U) #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ #define FLASH_SR_STRBERR_Pos (19U) #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ #define FLASH_SR_INCERR_Pos (20U) #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ #define FLASH_SR_OBKERR_Pos (21U) #define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ #define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ #define FLASH_SR_OBKWERR_Pos (22U) #define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ #define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ #define FLASH_SR_OPTCHANGEERR_Pos (23U) #define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ #define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ #define FLASH_CR_PG_Pos (1U) #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ #define FLASH_CR_SER_Pos (2U) #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ #define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ #define FLASH_CR_BER_Pos (3U) #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ #define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ #define FLASH_CR_FW_Pos (4U) #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ #define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ #define FLASH_CR_START_Pos (5U) #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ #define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ #define FLASH_CR_SNB_Pos (6U) #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ #define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ #define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ #define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ #define FLASH_CR_MER_Pos (15U) #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ #define FLASH_CR_EOPIE_Pos (16U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ #define FLASH_CR_WRPERRIE_Pos (17U) #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ #define FLASH_CR_PGSERRIE_Pos (18U) #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ #define FLASH_CR_STRBERRIE_Pos (19U) #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ #define FLASH_CR_INCERRIE_Pos (20U) #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ #define FLASH_CR_OBKERRIE_Pos (21U) #define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ #define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ #define FLASH_CR_OBKWERRIE_Pos (22U) #define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ #define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ #define FLASH_CR_OPTCHANGEERRIE_Pos (23U) #define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ #define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ #define FLASH_CR_INV_Pos (29U) #define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ #define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ #define FLASH_CR_BKSEL_Pos (31U) #define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ #define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ /******************* Bits definition for FLASH_CCR register *******************/ #define FLASH_CCR_CLR_EOP_Pos (16U) #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ #define FLASH_CCR_CLR_WRPERR_Pos (17U) #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ #define FLASH_CCR_CLR_PGSERR_Pos (18U) #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ #define FLASH_CCR_CLR_STRBERR_Pos (19U) #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ #define FLASH_CCR_CLR_INCERR_Pos (20U) #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ #define FLASH_CCR_CLR_OBKERR_Pos (21U) #define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ #define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ #define FLASH_CCR_CLR_OBKWERR_Pos (22U) #define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ #define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ #define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) #define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ #define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ /****************** Bits definition for FLASH_PRIVCFGR register ***********/ #define FLASH_PRIVCFGR_SPRIV_Pos (0U) #define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ #define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ #define FLASH_PRIVCFGR_NSPRIV_Pos (1U) #define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ #define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ /****************** Bits definition for FLASH_OBKCFGR register *****************/ #define FLASH_OBKCFGR_LOCK_Pos (0U) #define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ #define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ #define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) #define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ #define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ #define FLASH_OBKCFGR_ALT_SECT_Pos (2U) #define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ #define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ #define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) #define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ #define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ #define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) #define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ #define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ /****************** Bits definition for FLASH_HDPEXTR register *****************/ #define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) #define FLASH_HDPEXTR_HDP1_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000001F */ #define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ #define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) #define FLASH_HDPEXTR_HDP2_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x001F0000 */ #define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ /******************* Bits definition for FLASH_OPTSR register ***************/ #define FLASH_OPTSR_BOR_LEV_Pos (0U) #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ #define FLASH_OPTSR_BORH_EN_Pos (2U) #define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ #define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ #define FLASH_OPTSR_IWDG_SW_Pos (3U) #define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ #define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ #define FLASH_OPTSR_WWDG_SW_Pos (4U) #define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ #define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ #define FLASH_OPTSR_NRST_STOP_Pos (6U) #define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ #define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ #define FLASH_OPTSR_NRST_STDBY_Pos (7U) #define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ #define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ #define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) #define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ #define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ #define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) #define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ #define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ #define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) #define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ #define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ #define FLASH_OPTSR_IWDG_STOP_Pos (20U) #define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ #define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ #define FLASH_OPTSR_IWDG_STDBY_Pos (21U) #define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ #define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ #define FLASH_OPTSR_BOOT_UBE_Pos (22U) #define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ #define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ #define FLASH_OPTSR_SWAP_BANK_Pos (31U) #define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ #define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ /******************* Bits definition for FLASH_EPOCHR register ***************/ #define FLASH_EPOCHR_EPOCH_Pos (0U) #define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ #define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ /******************* Bits definition for FLASH_OPTSR2 register ***************/ #define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) #define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ #define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ #define FLASH_OPTSR2_SRAM2_RST_Pos (3U) #define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ #define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ #define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) #define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ #define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ #define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) #define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ #define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ #define FLASH_OPTSR2_USBPD_DIS_Pos (8U) #define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ #define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ #define FLASH_OPTSR2_TZEN_Pos (24U) #define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ #define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ /**************** Bits definition for FLASH_BOOTR register **********************/ #define FLASH_BOOTR_BOOT_LOCK_Pos (0U) #define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ #define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ #define FLASH_BOOTR_BOOTADD_Pos (8U) #define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ #define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ /**************** Bits definition for FLASH_PRIVBBR register *******************/ #define FLASH_PRIVBBR_PRIVBB_Pos (0U) #define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ #define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ /***************** Bits definition for FLASH_SECWMR register ********************/ #define FLASH_SECWMR_SECWM_STRT_Pos (0U) #define FLASH_SECWMR_SECWM_STRT_Msk (0x1FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000001F */ #define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ #define FLASH_SECWMR_SECWM_END_Pos (16U) #define FLASH_SECWMR_SECWM_END_Msk (0x1FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x001F0000 */ #define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ /***************** Bits definition for FLASH_WRPR register *********************/ #define FLASH_WRPR_WRPSG_Pos (0U) #define FLASH_WRPR_WRPSG_Msk (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */ #define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ /***************** Bits definition for FLASH_EDATA register ********************/ #define FLASH_EDATAR_EDATA_STRT_Pos (0U) #define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ #define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ #define FLASH_EDATAR_EDATA_EN_Pos (15U) #define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ #define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ /***************** Bits definition for FLASH_HDPR register ********************/ #define FLASH_HDPR_HDP_STRT_Pos (0U) #define FLASH_HDPR_HDP_STRT_Msk (0x1FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000001F */ #define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ #define FLASH_HDPR_HDP_END_Pos (16U) #define FLASH_HDPR_HDP_END_Msk (0x1FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x001F0000 */ #define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ /******************* Bits definition for FLASH_ECCR register ***************/ #define FLASH_ECCR_ADDR_ECC_Pos (0U) #define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ #define FLASH_ECCR_OBK_ECC_Pos (20U) #define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ #define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ #define FLASH_ECCR_DATA_ECC_Pos (21U) #define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ #define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ #define FLASH_ECCR_BK_ECC_Pos (22U) #define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ #define FLASH_ECCR_SYSF_ECC_Pos (23U) #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ #define FLASH_ECCR_OTP_ECC_Pos (24U) #define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ #define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ #define FLASH_ECCR_ECCIE_Pos (25U) #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ #define FLASH_ECCR_ECCC_Pos (30U) #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ #define FLASH_ECCR_ECCD_Pos (31U) #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ /******************* Bits definition for FLASH_ECCDR register ***************/ #define FLASH_ECCDR_FAIL_DATA_Pos (0U) #define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ #define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ /******************************************************************************/ /* */ /* Flexible Memory Controller */ /* */ /******************************************************************************/ /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ #define RTC_ALRMAR_SU_Pos (0U) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ #define RTC_ALRMAR_ST_Pos (4U) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ #define RTC_ALRMAR_MSK1_Pos (7U) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk #define RTC_ALRMAR_MNU_Pos (8U) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ #define RTC_ALRMAR_MNT_Pos (12U) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ #define RTC_ALRMAR_MSK2_Pos (15U) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk #define RTC_ALRMAR_HU_Pos (16U) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ #define RTC_ALRMAR_HT_Pos (20U) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ #define RTC_ALRMAR_PM_Pos (22U) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk #define RTC_ALRMAR_MSK3_Pos (23U) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk #define RTC_ALRMAR_DU_Pos (24U) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ #define RTC_ALRMAR_DT_Pos (28U) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ #define RTC_ALRMAR_WDSEL_Pos (30U) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk #define RTC_ALRMAR_MSK4_Pos (31U) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_SS_Pos (0U) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk #define RTC_ALRMASSR_MASKSS_Pos (24U) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ #define RTC_ALRMASSR_SSCLR_Pos (31U) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ #define RTC_ALRMBR_SU_Pos (0U) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ #define RTC_ALRMBR_ST_Pos (4U) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ #define RTC_ALRMBR_MSK1_Pos (7U) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk #define RTC_ALRMBR_MNU_Pos (8U) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ #define RTC_ALRMBR_MNT_Pos (12U) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ #define RTC_ALRMBR_MSK2_Pos (15U) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk #define RTC_ALRMBR_HU_Pos (16U) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ #define RTC_ALRMBR_HT_Pos (20U) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ #define RTC_ALRMBR_PM_Pos (22U) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk #define RTC_ALRMBR_MSK3_Pos (23U) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk #define RTC_ALRMBR_DU_Pos (24U) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ #define RTC_ALRMBR_DT_Pos (28U) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ #define RTC_ALRMBR_WDSEL_Pos (30U) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk #define RTC_ALRMBR_MSK4_Pos (31U) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ #define RTC_ALRMBSSR_SS_Pos (0U) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk #define RTC_ALRMBSSR_MASKSS_Pos (24U) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ #define RTC_ALRMBSSR_SSCLR_Pos (31U) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ #define RTC_SR_ALRAF_Pos (0U) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk #define RTC_SR_ALRBF_Pos (1U) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk #define RTC_SR_WUTF_Pos (2U) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk #define RTC_SR_TSF_Pos (3U) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk #define RTC_SR_TSOVF_Pos (4U) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk #define RTC_SR_ITSF_Pos (5U) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk #define RTC_SR_SSRUF_Pos (6U) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ #define RTC_MISR_ALRAMF_Pos (0U) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk #define RTC_MISR_ALRBMF_Pos (1U) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk #define RTC_MISR_WUTMF_Pos (2U) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk #define RTC_MISR_TSMF_Pos (3U) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk #define RTC_MISR_TSOVMF_Pos (4U) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk #define RTC_MISR_ITSMF_Pos (5U) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk #define RTC_MISR_SSRUMF_Pos (6U) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ #define RTC_SMISR_ALRAMF_Pos (0U) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk #define RTC_SMISR_ALRBMF_Pos (1U) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk #define RTC_SMISR_WUTMF_Pos (2U) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk #define RTC_SMISR_TSMF_Pos (3U) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk #define RTC_SMISR_TSOVMF_Pos (4U) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk #define RTC_SMISR_ITSMF_Pos (5U) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk #define RTC_SMISR_SSRUMF_Pos (6U) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ #define RTC_SCR_CALRAF_Pos (0U) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk #define RTC_SCR_CALRBF_Pos (1U) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk #define RTC_SCR_CWUTF_Pos (2U) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk #define RTC_SCR_CTSF_Pos (3U) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk #define RTC_SCR_CTSOVF_Pos (4U) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk #define RTC_SCR_CITSF_Pos (5U) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk #define RTC_SCR_CSSRUF_Pos (6U) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_OR register ******************/ #define RTC_OR_OUT2_RMP_Pos (0U) #define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ #define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ #define RTC_ALRABINR_SS_Pos (0U) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ #define RTC_ALRBBINR_SS_Pos (0U) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk /******************************************************************************/ /* */ /* Tamper and backup register (TAMP) */ /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ #define TAMP_CR1_TAMP1E_Pos (0U) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk #define TAMP_CR1_TAMP2E_Pos (1U) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk #define TAMP_CR1_TAMP3E_Pos (2U) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk #define TAMP_CR1_TAMP4E_Pos (3U) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk #define TAMP_CR1_TAMP5E_Pos (4U) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk #define TAMP_CR1_TAMP6E_Pos (5U) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk #define TAMP_CR1_TAMP7E_Pos (6U) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk #define TAMP_CR1_TAMP8E_Pos (7U) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk #define TAMP_CR1_ITAMP1E_Pos (16U) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk #define TAMP_CR1_ITAMP2E_Pos (17U) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk #define TAMP_CR1_ITAMP3E_Pos (18U) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk #define TAMP_CR1_ITAMP4E_Pos (19U) #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk #define TAMP_CR1_ITAMP5E_Pos (20U) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk #define TAMP_CR1_ITAMP6E_Pos (21U) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk #define TAMP_CR1_ITAMP7E_Pos (22U) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk #define TAMP_CR1_ITAMP8E_Pos (23U) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk #define TAMP_CR1_ITAMP9E_Pos (24U) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk #define TAMP_CR1_ITAMP11E_Pos (26U) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk #define TAMP_CR1_ITAMP12E_Pos (27U) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk #define TAMP_CR1_ITAMP13E_Pos (28U) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk #define TAMP_CR1_ITAMP15E_Pos (30U) #define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ #define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ #define TAMP_CR2_TAMP1NOERASE_Pos (0U) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk #define TAMP_CR2_TAMP2NOERASE_Pos (1U) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk #define TAMP_CR2_TAMP3NOERASE_Pos (2U) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk #define TAMP_CR2_TAMP4NOERASE_Pos (3U) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk #define TAMP_CR2_TAMP5NOERASE_Pos (4U) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk #define TAMP_CR2_TAMP6NOERASE_Pos (5U) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk #define TAMP_CR2_TAMP7NOERASE_Pos (6U) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk #define TAMP_CR2_TAMP8NOERASE_Pos (7U) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk #define TAMP_CR2_TAMP1MSK_Pos (16U) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk #define TAMP_CR2_TAMP2MSK_Pos (17U) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk #define TAMP_CR2_TAMP3MSK_Pos (18U) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk #define TAMP_CR2_BKBLOCK_Pos (22U) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk #define TAMP_CR2_BKERASE_Pos (23U) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk #define TAMP_CR2_TAMP1TRG_Pos (24U) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk #define TAMP_CR2_TAMP2TRG_Pos (25U) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk #define TAMP_CR2_TAMP3TRG_Pos (26U) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk #define TAMP_CR2_TAMP4TRG_Pos (27U) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk #define TAMP_CR2_TAMP5TRG_Pos (28U) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk #define TAMP_CR2_TAMP6TRG_Pos (29U) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk #define TAMP_CR2_TAMP7TRG_Pos (30U) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk #define TAMP_CR2_TAMP8TRG_Pos (31U) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ #define TAMP_CR3_ITAMP1NOER_Pos (0U) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk #define TAMP_CR3_ITAMP2NOER_Pos (1U) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk #define TAMP_CR3_ITAMP3NOER_Pos (2U) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk #define TAMP_CR3_ITAMP4NOER_Pos (3U) #define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ #define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk #define TAMP_CR3_ITAMP5NOER_Pos (4U) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk #define TAMP_CR3_ITAMP6NOER_Pos (5U) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk #define TAMP_CR3_ITAMP9NOER_Pos (8U) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk #define TAMP_CR3_ITAMP11NOER_Pos (10U) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk #define TAMP_CR3_ITAMP12NOER_Pos (11U) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk #define TAMP_CR3_ITAMP13NOER_Pos (12U) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk #define TAMP_CR3_ITAMP15NOER_Pos (14U) #define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ #define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ #define TAMP_FLTCR_TAMPFREQ_Pos (0U) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ #define TAMP_FLTCR_TAMPFLT_Pos (3U) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ #define TAMP_FLTCR_TAMPPRCH_Pos (5U) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ #define TAMP_FLTCR_TAMPPUDIS_Pos (7U) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ #define TAMP_ATCR1_TAMP1AM_Pos (0U) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk #define TAMP_ATCR1_TAMP2AM_Pos (1U) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk #define TAMP_ATCR1_TAMP3AM_Pos (2U) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk #define TAMP_ATCR1_TAMP4AM_Pos (3U) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk #define TAMP_ATCR1_TAMP5AM_Pos (4U) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk #define TAMP_ATCR1_TAMP6AM_Pos (5U) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk #define TAMP_ATCR1_TAMP7AM_Pos (6U) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk #define TAMP_ATCR1_TAMP8AM_Pos (7U) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk #define TAMP_ATCR1_ATOSEL1_Pos (8U) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR1_ATOSEL2_Pos (10U) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR1_ATOSEL3_Pos (12U) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ #define TAMP_ATCR1_ATOSEL4_Pos (14U) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ #define TAMP_ATCR1_ATCKSEL_Pos (16U) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ #define TAMP_ATCR1_ATPER_Pos (24U) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ #define TAMP_ATCR1_ATOSHARE_Pos (30U) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk #define TAMP_ATCR1_FLTEN_Pos (31U) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ #define TAMP_ATSEEDR_SEED_Pos (0U) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ #define TAMP_ATOR_PRNG_Pos (0U) #define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ #define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ #define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ #define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ #define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ #define TAMP_ATOR_SEEDF_Pos (14U) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk #define TAMP_ATOR_INITS_Pos (15U) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ #define TAMP_ATCR2_ATOSEL1_Pos (8U) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ #define TAMP_ATCR2_ATOSEL2_Pos (11U) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ #define TAMP_ATCR2_ATOSEL3_Pos (14U) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ #define TAMP_ATCR2_ATOSEL4_Pos (17U) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ #define TAMP_ATCR2_ATOSEL5_Pos (20U) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ #define TAMP_ATCR2_ATOSEL6_Pos (23U) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ #define TAMP_ATCR2_ATOSEL7_Pos (26U) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ #define TAMP_ATCR2_ATOSEL8_Pos (29U) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ #define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ #define TAMP_SECCFGR_BKPRWSEC_Pos (0U) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ #define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ #define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ #define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ #define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ #define TAMP_SECCFGR_CNT1SEC_Pos (15U) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk #define TAMP_SECCFGR_BKPWSEC_Pos (16U) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ #define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ #define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ #define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ #define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ #define TAMP_SECCFGR_BHKLOCK_Pos (30U) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk #define TAMP_SECCFGR_TAMPSEC_Pos (31U) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ #define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk #define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk #define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk #define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ #define TAMP_IER_TAMP1IE_Pos (0U) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk #define TAMP_IER_TAMP2IE_Pos (1U) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk #define TAMP_IER_TAMP3IE_Pos (2U) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk #define TAMP_IER_TAMP4IE_Pos (3U) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk #define TAMP_IER_TAMP5IE_Pos (4U) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk #define TAMP_IER_TAMP6IE_Pos (5U) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk #define TAMP_IER_TAMP7IE_Pos (6U) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk #define TAMP_IER_TAMP8IE_Pos (7U) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk #define TAMP_IER_ITAMP1IE_Pos (16U) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk #define TAMP_IER_ITAMP2IE_Pos (17U) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk #define TAMP_IER_ITAMP3IE_Pos (18U) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk #define TAMP_IER_ITAMP4IE_Pos (19U) #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk #define TAMP_IER_ITAMP5IE_Pos (20U) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk #define TAMP_IER_ITAMP6IE_Pos (21U) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk #define TAMP_IER_ITAMP7IE_Pos (22U) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk #define TAMP_IER_ITAMP8IE_Pos (23U) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk #define TAMP_IER_ITAMP9IE_Pos (24U) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk #define TAMP_IER_ITAMP11IE_Pos (26U) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk #define TAMP_IER_ITAMP12IE_Pos (27U) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk #define TAMP_IER_ITAMP13IE_Pos (28U) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk #define TAMP_IER_ITAMP15IE_Pos (30U) #define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ #define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk /******************** Bits definition for TAMP_SR register *****************/ #define TAMP_SR_TAMP1F_Pos (0U) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk #define TAMP_SR_TAMP2F_Pos (1U) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk #define TAMP_SR_TAMP3F_Pos (2U) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk #define TAMP_SR_TAMP4F_Pos (3U) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk #define TAMP_SR_TAMP5F_Pos (4U) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk #define TAMP_SR_TAMP6F_Pos (5U) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk #define TAMP_SR_TAMP7F_Pos (6U) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk #define TAMP_SR_TAMP8F_Pos (7U) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk #define TAMP_SR_ITAMP1F_Pos (16U) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk #define TAMP_SR_ITAMP2F_Pos (17U) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk #define TAMP_SR_ITAMP3F_Pos (18U) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk #define TAMP_SR_ITAMP4F_Pos (19U) #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk #define TAMP_SR_ITAMP5F_Pos (20U) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk #define TAMP_SR_ITAMP6F_Pos (21U) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk #define TAMP_SR_ITAMP7F_Pos (22U) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk #define TAMP_SR_ITAMP8F_Pos (23U) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk #define TAMP_SR_ITAMP9F_Pos (24U) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk #define TAMP_SR_ITAMP11F_Pos (26U) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk #define TAMP_SR_ITAMP12F_Pos (27U) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk #define TAMP_SR_ITAMP13F_Pos (28U) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk #define TAMP_SR_ITAMP15F_Pos (30U) #define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ #define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk /******************** Bits definition for TAMP_MISR register ****************/ #define TAMP_MISR_TAMP1MF_Pos (0U) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk #define TAMP_MISR_TAMP2MF_Pos (1U) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk #define TAMP_MISR_TAMP3MF_Pos (2U) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk #define TAMP_MISR_TAMP4MF_Pos (3U) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk #define TAMP_MISR_TAMP5MF_Pos (4U) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk #define TAMP_MISR_TAMP6MF_Pos (5U) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk #define TAMP_MISR_TAMP7MF_Pos (6U) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk #define TAMP_MISR_TAMP8MF_Pos (7U) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk #define TAMP_MISR_ITAMP1MF_Pos (16U) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk #define TAMP_MISR_ITAMP2MF_Pos (17U) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk #define TAMP_MISR_ITAMP3MF_Pos (18U) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk #define TAMP_MISR_ITAMP4MF_Pos (19U) #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk #define TAMP_MISR_ITAMP5MF_Pos (20U) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk #define TAMP_MISR_ITAMP6MF_Pos (21U) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk #define TAMP_MISR_ITAMP7MF_Pos (22U) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk #define TAMP_MISR_ITAMP8MF_Pos (23U) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk #define TAMP_MISR_ITAMP9MF_Pos (24U) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk #define TAMP_MISR_ITAMP11MF_Pos (26U) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk #define TAMP_MISR_ITAMP12MF_Pos (27U) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk #define TAMP_MISR_ITAMP13MF_Pos (28U) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk #define TAMP_MISR_ITAMP15MF_Pos (30U) #define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ #define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ #define TAMP_SMISR_TAMP1MF_Pos (0U) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk #define TAMP_SMISR_TAMP2MF_Pos (1U) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk #define TAMP_SMISR_TAMP3MF_Pos (2U) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk #define TAMP_SMISR_TAMP4MF_Pos (3U) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk #define TAMP_SMISR_TAMP5MF_Pos (4U) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk #define TAMP_SMISR_TAMP6MF_Pos (5U) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk #define TAMP_SMISR_TAMP7MF_Pos (6U) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk #define TAMP_SMISR_TAMP8MF_Pos (7U) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk #define TAMP_SMISR_ITAMP1MF_Pos (16U) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk #define TAMP_SMISR_ITAMP2MF_Pos (17U) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk #define TAMP_SMISR_ITAMP3MF_Pos (18U) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk #define TAMP_SMISR_ITAMP4MF_Pos (19U) #define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ #define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk #define TAMP_SMISR_ITAMP5MF_Pos (20U) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk #define TAMP_SMISR_ITAMP6MF_Pos (21U) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk #define TAMP_SMISR_ITAMP7MF_Pos (22U) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk #define TAMP_SMISR_ITAMP8MF_Pos (23U) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk #define TAMP_SMISR_ITAMP9MF_Pos (24U) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk #define TAMP_SMISR_ITAMP11MF_Pos (26U) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk #define TAMP_SMISR_ITAMP12MF_Pos (27U) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk #define TAMP_SMISR_ITAMP13MF_Pos (28U) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk #define TAMP_SMISR_ITAMP15MF_Pos (30U) #define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ #define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ #define TAMP_SCR_CTAMP1F_Pos (0U) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk #define TAMP_SCR_CTAMP2F_Pos (1U) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk #define TAMP_SCR_CTAMP3F_Pos (2U) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk #define TAMP_SCR_CTAMP4F_Pos (3U) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk #define TAMP_SCR_CTAMP5F_Pos (4U) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk #define TAMP_SCR_CTAMP6F_Pos (5U) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk #define TAMP_SCR_CTAMP7F_Pos (6U) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk #define TAMP_SCR_CTAMP8F_Pos (7U) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk #define TAMP_SCR_CITAMP1F_Pos (16U) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk #define TAMP_SCR_CITAMP2F_Pos (17U) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk #define TAMP_SCR_CITAMP3F_Pos (18U) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk #define TAMP_SCR_CITAMP4F_Pos (19U) #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk #define TAMP_SCR_CITAMP5F_Pos (20U) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk #define TAMP_SCR_CITAMP6F_Pos (21U) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk #define TAMP_SCR_CITAMP7F_Pos (22U) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk #define TAMP_SCR_CITAMP8F_Pos (23U) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk #define TAMP_SCR_CITAMP9F_Pos (24U) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk #define TAMP_SCR_CITAMP11F_Pos (26U) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk #define TAMP_SCR_CITAMP12F_Pos (27U) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk #define TAMP_SCR_CITAMP13F_Pos (28U) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk #define TAMP_SCR_CITAMP15F_Pos (30U) #define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ #define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk /******************** Bits definition for TAMP_COUNT1R register ***************/ #define TAMP_COUNT1R_COUNT_Pos (0U) #define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ #define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk /******************** Bits definition for TAMP_OR register ***************/ #define TAMP_OR_OUT3_RMP_Pos (1U) #define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ #define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk #define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ #define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ #define TAMP_OR_OUT5_RMP_Pos (3U) #define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ #define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk #define TAMP_OR_IN2_RMP_Pos (8U) #define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ #define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk #define TAMP_OR_IN3_RMP_Pos (9U) #define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ #define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk #define TAMP_OR_IN4_RMP_Pos (10U) #define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ #define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk /******************** Bits definition for TAMP_ERCFG register ***************/ #define TAMP_ERCFGR_ERCFG0_Pos (0U) #define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ #define TAMP_BKP0R_Pos (0U) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ #define TAMP_BKP1R_Pos (0U) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ #define TAMP_BKP2R_Pos (0U) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ #define TAMP_BKP3R_Pos (0U) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ #define TAMP_BKP4R_Pos (0U) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ #define TAMP_BKP5R_Pos (0U) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ #define TAMP_BKP6R_Pos (0U) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ #define TAMP_BKP7R_Pos (0U) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ #define TAMP_BKP8R_Pos (0U) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ #define TAMP_BKP9R_Pos (0U) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ #define TAMP_BKP10R_Pos (0U) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ #define TAMP_BKP11R_Pos (0U) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ #define TAMP_BKP12R_Pos (0U) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ #define TAMP_BKP13R_Pos (0U) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ #define TAMP_BKP14R_Pos (0U) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ #define TAMP_BKP15R_Pos (0U) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ #define TAMP_BKP16R_Pos (0U) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ #define TAMP_BKP17R_Pos (0U) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ #define TAMP_BKP18R_Pos (0U) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ #define TAMP_BKP19R_Pos (0U) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ #define TAMP_BKP20R_Pos (0U) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ #define TAMP_BKP21R_Pos (0U) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ #define TAMP_BKP22R_Pos (0U) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ #define TAMP_BKP23R_Pos (0U) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ #define TAMP_BKP24R_Pos (0U) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ #define TAMP_BKP25R_Pos (0U) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ #define TAMP_BKP26R_Pos (0U) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ #define TAMP_BKP27R_Pos (0U) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ #define TAMP_BKP28R_Pos (0U) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ #define TAMP_BKP29R_Pos (0U) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ #define TAMP_BKP30R_Pos (0U) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ #define TAMP_BKP31R_Pos (0U) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk /******************************************************************************/ /* */ /* SBS */ /* */ /******************************************************************************/ /******************** Bit definition for SBS_HDPLCR register *****************/ #define SBS_HDPLCR_INCR_HDPL_Pos (0U) #define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ #define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ /******************** Bit definition for SBS_HDPLSR register *****************/ #define SBS_HDPLSR_HDPL_Pos (0U) #define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ #define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ /******************** Bit definition for SBS_NEXTHDPLCR register *****************/ #define SBS_NEXTHDPLCR_NEXTHDPL_Pos (0U) #define SBS_NEXTHDPLCR_NEXTHDPL_Msk (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000003 */ #define SBS_NEXTHDPLCR_NEXTHDPL SBS_NEXTHDPLCR_NEXTHDPL_Msk /*!< NEXTHDPL value. */ #define SBS_NEXTHDPLCR_NEXTHDPL_0 (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000001 */ #define SBS_NEXTHDPLCR_NEXTHDPL_1 (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000002 */ /******************** Bit definition for SBS_DBGCR register *****************/ #define SBS_DBGCR_AP_UNLOCK_Pos (0U) #define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ #define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ #define SBS_DBGCR_DBG_UNLOCK_Pos (8U) #define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ #define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ #define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) #define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ #define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ #define SBS_DBGCR_DBG_AUTH_SEC_Pos (24U) #define SBS_DBGCR_DBG_AUTH_SEC_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */ #define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-secured and secured debugs. */ /******************** Bit definition for SBS_DBGLCKR register *****************/ #define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) #define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ #define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ /******************** Bit definition for SBS_RSSCMDR register ***************/ #define SBS_RSSCMDR_RSSCMD_Pos (0U) #define SBS_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ #define SBS_RSSCMDR_RSSCMD SBS_RSSCMDR_RSSCMD_Msk /*!< command to be executed by the RSS. */ /******************** Bit definition for SBS_EPOCHSELCR register ************/ #define SBS_EPOCHSELCR_EPOCH_SEL_Pos (0U) #define SBS_EPOCHSELCR_EPOCH_SEL_Msk (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000003 */ #define SBS_EPOCHSELCR_EPOCH_SEL SBS_EPOCHSELCR_EPOCH_SEL_Msk /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys */ #define SBS_EPOCHSELCR_EPOCH_SEL_0 (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000001 */ #define SBS_EPOCHSELCR_EPOCH_SEL_1 (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000002 */ /****************** Bit definition for SBS_PMCR register ****************/ #define SBS_PMCR_PB6_FMP_Pos (16U) #define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ #define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ #define SBS_PMCR_PB7_FMP_Pos (17U) #define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ #define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ #define SBS_PMCR_PB8_FMP_Pos (18U) #define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ #define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ #define SBS_PMCR_PB9_FMP_Pos (19U) #define SBS_PMCR_PB9_FMP_Msk (0x1UL << SBS_PMCR_PB9_FMP_Pos) /*!< 0x00080000 */ #define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode Plus command on PB(9) */ /****************** Bit definition for SBS_FPUIMR register ***************/ #define SBS_FPUIMR_FPU_IE_Pos (0U) #define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ #define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ #define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ #define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ #define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ #define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ #define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ #define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ /****************** Bit definition for SBS_MESR register ****************/ #define SBS_MESR_MCLR_Pos (0U) #define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ #define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ #define SBS_MESR_IPMEE_Pos (16U) #define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ #define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ /****************** Bit definition for SBS_CCCSR register ****************/ #define SBS_CCCSR_EN1_Pos (0U) #define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ #define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ #define SBS_CCCSR_CS1_Pos (1U) #define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ #define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ #define SBS_CCCSR_EN2_Pos (2U) #define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ #define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ #define SBS_CCCSR_CS2_Pos (3U) #define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ #define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ #define SBS_CCCSR_RDY1_Pos (8U) #define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ #define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ #define SBS_CCCSR_RDY2_Pos (9U) #define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ #define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ /****************** Bit definition for SBS_CCVALR register ****************/ #define SBS_CCVALR_ANSRC1_Pos (0U) #define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ #define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ #define SBS_CCVALR_APSRC1_Pos (4U) #define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ #define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ #define SBS_CCVALR_ANSRC2_Pos (8U) #define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ #define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ #define SBS_CCVALR_APSRC2_Pos (12U) #define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ #define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ /****************** Bit definition for SBS_CCSWCR register ****************/ #define SBS_CCSWCR_SW_ANSRC1_Pos (0U) #define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ #define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ #define SBS_CCSWCR_SW_APSRC1_Pos (4U) #define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ #define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ #define SBS_CCSWCR_SW_ANSRC2_Pos (8U) #define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ #define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ #define SBS_CCSWCR_SW_APSRC2_Pos (12U) #define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ #define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ /****************** Bit definition for SBS_CFGR2 register ****************/ #define SBS_CFGR2_CLL_Pos (0U) #define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ #define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ #define SBS_CFGR2_SEL_Pos (1U) #define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ #define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ #define SBS_CFGR2_PVDL_Pos (2U) #define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ #define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ #define SBS_CFGR2_ECCL_Pos (3U) #define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ #define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ /******************** Bit definition for SBS_SECCFGR register ***************/ #define SBS_SECCFGR_SBSSEC_Pos (0U) #define SBS_SECCFGR_SBSSEC_Msk (0x1UL << SBS_SECCFGR_SBSSEC_Pos) /*!< 0x00000001 */ #define SBS_SECCFGR_SBSSEC SBS_SECCFGR_SBSSEC_Msk /*!< SBS clock control security enable */ #define SBS_SECCFGR_CLASSBSEC_Pos (1U) #define SBS_SECCFGR_CLASSBSEC_Msk (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */ #define SBS_SECCFGR_CLASSBSEC SBS_SECCFGR_CLASSBSEC_Msk /*!< ClassB SBS security enable */ #define SBS_SECCFGR_FPUSEC_Pos (3U) #define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */ #define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */ /****************** Bit definition for SBS_CNSLCKR register **************/ #define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) #define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ #define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ #define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) #define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ #define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ /****************** Bit definition for SBS_CSLCKR register ***************/ #define SBS_CSLCKR_LOCKSVTAIRCR_Pos (0U) #define SBS_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ #define SBS_CSLCKR_LOCKSVTAIRCR SBS_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ #define SBS_CSLCKR_LOCKSMPU_Pos (1U) #define SBS_CSLCKR_LOCKSMPU_Msk (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ #define SBS_CSLCKR_LOCKSMPU SBS_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ #define SBS_CSLCKR_LOCKSAU_Pos (2U) #define SBS_CSLCKR_LOCKSAU_Msk (0x1UL << SBS_CSLCKR_LOCKSAU_Pos) /*!< 0x00000004 */ #define SBS_CSLCKR_LOCKSAU SBS_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */ /****************** Bit definition for SBS_ECCNMIR register ***************/ #define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) #define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ #define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ /*****************************************************************************/ /* */ /* Global TrustZone Control */ /* */ /*****************************************************************************/ /******************* Bits definition for GTZC_TZSC_CR register ******************/ #define GTZC_TZSC_CR_LCK_Pos (0U) #define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ /******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ #define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) #define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) #define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) #define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk #define GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) #define GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) #define GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk #define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) #define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) #define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk /******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ #define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) #define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) #define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk /******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ /******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/ /*************** Bits definition for register x=1 (TZSC1) *************/ #define GTZC_CFGR1_TIM2_Pos (0U) #define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) #define GTZC_CFGR1_TIM3_Pos (1U) #define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) #define GTZC_CFGR1_TIM4_Pos (2U) #define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) #define GTZC_CFGR1_TIM5_Pos (3U) #define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) #define GTZC_CFGR1_TIM6_Pos (4U) #define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) #define GTZC_CFGR1_TIM7_Pos (5U) #define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) #define GTZC_CFGR1_TIM12_Pos (6U) #define GTZC_CFGR1_TIM12_Msk (0x01UL << GTZC_CFGR1_TIM12_Pos) #define GTZC_CFGR1_WWDG_Pos (9U) #define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) #define GTZC_CFGR1_IWDG_Pos (10U) #define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) #define GTZC_CFGR1_SPI2_Pos (11U) #define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) #define GTZC_CFGR1_SPI3_Pos (12U) #define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) #define GTZC_CFGR1_USART2_Pos (13U) #define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) #define GTZC_CFGR1_USART3_Pos (14U) #define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) #define GTZC_CFGR1_UART4_Pos (15U) #define GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) #define GTZC_CFGR1_UART5_Pos (16U) #define GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) #define GTZC_CFGR1_I2C1_Pos (17U) #define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) #define GTZC_CFGR1_I2C2_Pos (18U) #define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) #define GTZC_CFGR1_I3C1_Pos (19U) #define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) #define GTZC_CFGR1_CRS_Pos (20U) #define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) #define GTZC_CFGR1_USART6_Pos (21U) #define GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) #define GTZC_CFGR1_HDMICEC_Pos (24U) #define GTZC_CFGR1_HDMICEC_Msk (0x01UL << GTZC_CFGR1_HDMICEC_Pos) #define GTZC_CFGR1_DAC1_Pos (25U) #define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) #define GTZC_CFGR1_DTS_Pos (30U) #define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) #define GTZC_CFGR1_LPTIM2_Pos (31U) #define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) /*************** Bits definition for register x=2 (TZSC1) *************/ #define GTZC_CFGR2_FDCAN1_Pos (0U) #define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) #define GTZC_CFGR2_FDCAN2_Pos (1U) #define GTZC_CFGR2_FDCAN2_Msk (0x01UL << GTZC_CFGR2_FDCAN2_Pos) #define GTZC_CFGR2_UCPD1_Pos (2U) #define GTZC_CFGR2_UCPD1_Msk (0x01UL << GTZC_CFGR2_UCPD1_Pos) #define GTZC_CFGR2_TIM1_Pos (8U) #define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) #define GTZC_CFGR2_SPI1_Pos (9U) #define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) #define GTZC_CFGR2_TIM8_Pos (10U) #define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) #define GTZC_CFGR2_USART1_Pos (11U) #define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) #define GTZC_CFGR2_TIM15_Pos (12U) #define GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) #define GTZC_CFGR2_SPI4_Pos (15U) #define GTZC_CFGR2_SPI4_Msk (0x01UL << GTZC_CFGR2_SPI4_Pos) #define GTZC_CFGR2_USB_Pos (19U) #define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) #define GTZC_CFGR2_LPUART1_Pos (25U) #define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) #define GTZC_CFGR2_I2C3_Pos (26U) #define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) #define GTZC_CFGR2_LPTIM1_Pos (28U) #define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) /*************** Bits definition for register x=3 (TZSC1) *************/ #define GTZC_CFGR3_VREFBUF_Pos (1U) #define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) #define GTZC_CFGR3_I3C2_Pos (2U) #define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) #define GTZC_CFGR3_CRC_Pos (8U) #define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) #define GTZC_CFGR3_ICACHE_REG_Pos (12U) #define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) #define GTZC_CFGR3_DCACHE1_REG_Pos (13U) #define GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) #define GTZC_CFGR3_ADC_Pos (14U) #define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) #define GTZC_CFGR3_DCMI_PSSI_Pos (15U) #define GTZC_CFGR3_DCMI_PSSI_Msk (0x01UL << GTZC_CFGR3_DCMI_PSSI_Pos) #define GTZC_CFGR3_HASH_Pos (17U) #define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) #define GTZC_CFGR3_RNG_Pos (18U) #define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) #define GTZC_CFGR3_SDMMC1_Pos (21U) #define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) #define GTZC_CFGR3_FMC_REG_Pos (23U) #define GTZC_CFGR3_FMC_REG_Msk (0x01UL << GTZC_CFGR3_FMC_REG_Pos) #define GTZC_CFGR3_OCTOSPI1_Pos (24U) #define GTZC_CFGR3_OCTOSPI1_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos) #define GTZC_CFGR3_RAMCFG_Pos (26U) #define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) /*************** Bits definition for register x=4 (TZSC1) *************/ #define GTZC_CFGR4_GPDMA1_Pos (0U) #define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) #define GTZC_CFGR4_GPDMA2_Pos (1U) #define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) #define GTZC_CFGR4_FLASH_Pos (2U) #define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) #define GTZC_CFGR4_FLASH_REG_Pos (3U) #define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) #define GTZC_CFGR4_SBS_Pos (6U) #define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) #define GTZC_CFGR4_RTC_Pos (7U) #define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) #define GTZC_CFGR4_TAMP_Pos (8U) #define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) #define GTZC_CFGR4_PWR_Pos (9U) #define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) #define GTZC_CFGR4_RCC_Pos (10U) #define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) #define GTZC_CFGR4_EXTI_Pos (11U) #define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) #define GTZC_CFGR4_TZSC_Pos (16U) #define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) #define GTZC_CFGR4_TZIC_Pos (17U) #define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) #define GTZC_CFGR4_OCTOSPI1_MEM_Pos (18U) #define GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) #define GTZC_CFGR4_FMC_MEM_Pos (19U) #define GTZC_CFGR4_FMC_MEM_Msk (0x01UL << GTZC_CFGR4_FMC_MEM_Pos) #define GTZC_CFGR4_BKPSRAM_Pos (20U) #define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) #define GTZC_CFGR4_SRAM1_Pos (24U) #define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) #define GTZC_CFGR4_MPCBB1_REG_Pos (25U) #define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) #define GTZC_CFGR4_SRAM2_Pos (26U) #define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) #define GTZC_CFGR4_MPCBB2_REG_Pos (27U) #define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) #define GTZC_CFGR4_SRAM3_Pos (28U) #define GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) #define GTZC_CFGR4_MPCBB3_REG_Pos (29U) #define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) /******************* Bits definition for GTZC_TZSC1_SECCFGR1 register ***************/ #define GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos #define GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk #define GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos #define GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk #define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos #define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk #define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos #define GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk #define GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos #define GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk #define GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos #define GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk #define GTZC_TZSC1_SECCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos #define GTZC_TZSC1_SECCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk #define GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos #define GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk #define GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos #define GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk #define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos #define GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk #define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos #define GTZC_TZSC1_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk #define GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos #define GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk #define GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos #define GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk #define GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos #define GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk #define GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos #define GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk #define GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos #define GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk #define GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos #define GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk #define GTZC_TZSC1_SECCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos #define GTZC_TZSC1_SECCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk #define GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos #define GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk #define GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos #define GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk #define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos #define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk #define GTZC_TZSC1_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos #define GTZC_TZSC1_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk #define GTZC_TZSC1_SECCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos #define GTZC_TZSC1_SECCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk #define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos #define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk /******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ #define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos #define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk #define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos #define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk #define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos #define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk #define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos #define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk #define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos #define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk #define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos #define GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk #define GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos #define GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk #define GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos #define GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk #define GTZC_TZSC1_SECCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos #define GTZC_TZSC1_SECCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk #define GTZC_TZSC1_SECCFGR2_USB_Pos GTZC_CFGR2_USB_Pos #define GTZC_TZSC1_SECCFGR2_USB_Msk GTZC_CFGR2_USB_Msk #define GTZC_TZSC1_SECCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos #define GTZC_TZSC1_SECCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk #define GTZC_TZSC1_SECCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos #define GTZC_TZSC1_SECCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk #define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos #define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk /******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ #define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos #define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk #define GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos #define GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk #define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos #define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk #define GTZC_TZSC1_SECCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos #define GTZC_TZSC1_SECCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk #define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos #define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk #define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos #define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk #define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos #define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk #define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos #define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk #define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos #define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk #define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos #define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk /******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ #define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk #define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos #define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk #define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos #define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk #define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos #define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos #define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos #define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk #define GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos #define GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk #define GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos #define GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk #define GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos #define GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk #define GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos #define GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk #define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos #define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk #define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos #define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk #define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos #define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk #define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos #define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk #define GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos #define GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk #define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos #define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk #define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos #define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk #define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos #define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk /******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk #define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos #define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk #define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos #define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk #define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos #define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk #define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos #define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk #define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos #define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk #define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos #define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk #define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos #define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk #define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos #define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk #define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos #define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk /******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ #define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos #define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk #define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos #define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk #define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos #define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk #define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos #define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk #define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos #define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk #define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos #define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk #define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos #define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk #define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos #define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk #define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos #define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk /******************* Bits definition for GTZC_TZIC_IER1 register ***************/ #define GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos #define GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk #define GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos #define GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk #define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos #define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk #define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos #define GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk #define GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos #define GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk #define GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos #define GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk #define GTZC_TZIC1_IER1_TIM12_Pos GTZC_CFGR1_TIM12_Pos #define GTZC_TZIC1_IER1_TIM12_Msk GTZC_CFGR1_TIM12_Msk #define GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos #define GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk #define GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos #define GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk #define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos #define GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk #define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos #define GTZC_TZIC1_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk #define GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos #define GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk #define GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos #define GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk #define GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos #define GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk #define GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos #define GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk #define GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos #define GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk #define GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos #define GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk #define GTZC_TZIC1_IER1_I3C1_Pos GTZC_CFGR1_I3C1_Pos #define GTZC_TZIC1_IER1_I3C1_Msk GTZC_CFGR1_I3C1_Msk #define GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos #define GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk #define GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos #define GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk #define GTZC_TZIC1_IER1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos #define GTZC_TZIC1_IER1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk #define GTZC_TZIC1_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos #define GTZC_TZIC1_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk #define GTZC_TZIC1_IER1_DTS_Pos GTZC_CFGR1_DTS_Pos #define GTZC_TZIC1_IER1_DTS_Msk GTZC_CFGR1_DTS_Msk #define GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos #define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk /******************* Bits definition for GTZC_TZIC_IER2 register ***************/ #define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos #define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk #define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos #define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk #define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos #define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk #define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos #define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk #define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos #define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk #define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos #define GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk #define GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos #define GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk #define GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos #define GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk #define GTZC_TZIC1_IER2_SPI4_Pos GTZC_CFGR2_SPI4_Pos #define GTZC_TZIC1_IER2_SPI4_Msk GTZC_CFGR2_SPI4_Msk #define GTZC_TZIC1_IER2_USB_Pos GTZC_CFGR2_USB_Pos #define GTZC_TZIC1_IER2_USB_Msk GTZC_CFGR2_USB_Msk #define GTZC_TZIC1_IER2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos #define GTZC_TZIC1_IER2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk #define GTZC_TZIC1_IER2_I2C3_Pos GTZC_CFGR2_I2C3_Pos #define GTZC_TZIC1_IER2_I2C3_Msk GTZC_CFGR2_I2C3_Msk #define GTZC_TZIC1_IER2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos #define GTZC_TZIC1_IER2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk /******************* Bits definition for GTZC_TZIC_IER3 register ***************/ #define GTZC_TZIC1_IER3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos #define GTZC_TZIC1_IER3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZIC1_IER3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk #define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos #define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk #define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk #define GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos #define GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk #define GTZC_TZIC1_IER3_ADC_Pos GTZC_CFGR3_ADC_Pos #define GTZC_TZIC1_IER3_ADC_Msk GTZC_CFGR3_ADC_Msk #define GTZC_TZIC1_IER3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos #define GTZC_TZIC1_IER3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk #define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos #define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk #define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos #define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk #define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos #define GTZC_TZIC1_IER3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk #define GTZC_TZIC1_IER3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos #define GTZC_TZIC1_IER3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk #define GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos #define GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk /******************* Bits definition for GTZC_TZIC_IER4 register ***************/ #define GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos #define GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk #define GTZC_TZIC1_IER4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos #define GTZC_TZIC1_IER4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk #define GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos #define GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk #define GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos #define GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk #define GTZC_TZIC1_IER4_SBS_Pos GTZC_CFGR4_SBS_Pos #define GTZC_TZIC1_IER4_SBS_Msk GTZC_CFGR4_SBS_Msk #define GTZC_TZIC1_IER4_RTC_Pos GTZC_CFGR4_RTC_Pos #define GTZC_TZIC1_IER4_RTC_Msk GTZC_CFGR4_RTC_Msk #define GTZC_TZIC1_IER4_TAMP_Pos GTZC_CFGR4_TAMP_Pos #define GTZC_TZIC1_IER4_TAMP_Msk GTZC_CFGR4_TAMP_Msk #define GTZC_TZIC1_IER4_PWR_Pos GTZC_CFGR4_PWR_Pos #define GTZC_TZIC1_IER4_PWR_Msk GTZC_CFGR4_PWR_Msk #define GTZC_TZIC1_IER4_RCC_Pos GTZC_CFGR4_RCC_Pos #define GTZC_TZIC1_IER4_RCC_Msk GTZC_CFGR4_RCC_Msk #define GTZC_TZIC1_IER4_EXTI_Pos GTZC_CFGR4_EXTI_Pos #define GTZC_TZIC1_IER4_EXTI_Msk GTZC_CFGR4_EXTI_Msk #define GTZC_TZIC1_IER4_TZSC_Pos GTZC_CFGR4_TZSC_Pos #define GTZC_TZIC1_IER4_TZSC_Msk GTZC_CFGR4_TZSC_Msk #define GTZC_TZIC1_IER4_TZIC_Pos GTZC_CFGR4_TZIC_Pos #define GTZC_TZIC1_IER4_TZIC_Msk GTZC_CFGR4_TZIC_Msk #define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos #define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk #define GTZC_TZIC1_IER4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos #define GTZC_TZIC1_IER4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk #define GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos #define GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk #define GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos #define GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk #define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos #define GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk #define GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos #define GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk #define GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos #define GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk #define GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos #define GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk #define GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos #define GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk /******************* Bits definition for GTZC_TZIC_SR1 register **************/ #define GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos #define GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk #define GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos #define GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk #define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos #define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk #define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos #define GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk #define GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos #define GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk #define GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos #define GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk #define GTZC_TZIC1_SR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos #define GTZC_TZIC1_SR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk #define GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos #define GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk #define GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos #define GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk #define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos #define GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk #define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos #define GTZC_TZIC1_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk #define GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos #define GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk #define GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos #define GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk #define GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos #define GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk #define GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos #define GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk #define GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos #define GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk #define GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos #define GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk #define GTZC_TZIC1_SR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos #define GTZC_TZIC1_SR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk #define GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos #define GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk #define GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos #define GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk #define GTZC_TZIC1_SR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos #define GTZC_TZIC1_SR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk #define GTZC_TZIC1_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos #define GTZC_TZIC1_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk #define GTZC_TZIC1_SR1_DTS_Pos GTZC_CFGR1_DTS_Pos #define GTZC_TZIC1_SR1_DTS_Msk GTZC_CFGR1_DTS_Msk #define GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos #define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk /******************* Bits definition for GTZC_TZIC_SR2 register **************/ #define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos #define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk #define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos #define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk #define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos #define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk #define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos #define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk #define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos #define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk #define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos #define GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk #define GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos #define GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk #define GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos #define GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk #define GTZC_TZIC1_SR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos #define GTZC_TZIC1_SR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk #define GTZC_TZIC1_SR2_USB_Pos GTZC_CFGR2_USB_Pos #define GTZC_TZIC1_SR2_USB_Msk GTZC_CFGR2_USB_Msk #define GTZC_TZIC1_SR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos #define GTZC_TZIC1_SR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk #define GTZC_TZIC1_SR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos #define GTZC_TZIC1_SR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk #define GTZC_TZIC1_SR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos #define GTZC_TZIC1_SR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk /******************* Bits definition for GTZC_TZIC_SR3 register **************/ #define GTZC_TZIC1_SR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos #define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk #define GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos #define GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk #define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk #define GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos #define GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk #define GTZC_TZIC1_SR3_ADC_Pos GTZC_CFGR3_ADC_Pos #define GTZC_TZIC1_SR3_ADC_Msk GTZC_CFGR3_ADC_Msk #define GTZC_TZIC1_SR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos #define GTZC_TZIC1_SR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk #define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos #define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk #define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos #define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk #define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos #define GTZC_TZIC1_SR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk #define GTZC_TZIC1_SR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos #define GTZC_TZIC1_SR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk #define GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos #define GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk /******************* Bits definition for GTZC_TZIC_SR4 register ***************/ #define GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos #define GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk #define GTZC_TZIC1_SR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos #define GTZC_TZIC1_SR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk #define GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos #define GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk #define GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos #define GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk #define GTZC_TZIC1_SR4_SBS_Pos GTZC_CFGR4_SBS_Pos #define GTZC_TZIC1_SR4_SBS_Msk GTZC_CFGR4_SBS_Msk #define GTZC_TZIC1_SR4_RTC_Pos GTZC_CFGR4_RTC_Pos #define GTZC_TZIC1_SR4_RTC_Msk GTZC_CFGR4_RTC_Msk #define GTZC_TZIC1_SR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos #define GTZC_TZIC1_SR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk #define GTZC_TZIC1_SR4_PWR_Pos GTZC_CFGR4_PWR_Pos #define GTZC_TZIC1_SR4_PWR_Msk GTZC_CFGR4_PWR_Msk #define GTZC_TZIC1_SR4_RCC_Pos GTZC_CFGR4_RCC_Pos #define GTZC_TZIC1_SR4_RCC_Msk GTZC_CFGR4_RCC_Msk #define GTZC_TZIC1_SR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos #define GTZC_TZIC1_SR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk #define GTZC_TZIC1_SR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos #define GTZC_TZIC1_SR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk #define GTZC_TZIC1_SR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos #define GTZC_TZIC1_SR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk #define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos #define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk #define GTZC_TZIC1_SR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos #define GTZC_TZIC1_SR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk #define GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos #define GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk #define GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos #define GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk #define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos #define GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk #define GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos #define GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk #define GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos #define GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk #define GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos #define GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk #define GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos #define GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk /****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ #define GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos #define GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk #define GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos #define GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk #define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos #define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk #define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos #define GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk #define GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos #define GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk #define GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos #define GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk #define GTZC_TZIC1_FCR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos #define GTZC_TZIC1_FCR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk #define GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos #define GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk #define GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos #define GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk #define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos #define GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk #define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos #define GTZC_TZIC1_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk #define GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos #define GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk #define GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos #define GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk #define GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos #define GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk #define GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos #define GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk #define GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos #define GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk #define GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos #define GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk #define GTZC_TZIC1_FCR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos #define GTZC_TZIC1_FCR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk #define GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos #define GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk #define GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos #define GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk #define GTZC_TZIC1_FCR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos #define GTZC_TZIC1_FCR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk #define GTZC_TZIC1_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos #define GTZC_TZIC1_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk #define GTZC_TZIC1_FCR1_DTS_Pos GTZC_CFGR1_DTS_Pos #define GTZC_TZIC1_FCR1_DTS_Msk GTZC_CFGR1_DTS_Msk #define GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos #define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk /******************* Bits definition for GTZC_TZIC_FCR2 register **************/ #define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos #define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk #define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos #define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk #define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos #define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk #define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos #define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk #define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos #define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk #define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos #define GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk #define GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos #define GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk #define GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos #define GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk #define GTZC_TZIC1_FCR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos #define GTZC_TZIC1_FCR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk #define GTZC_TZIC1_FCR2_USB_Pos GTZC_CFGR2_USB_Pos #define GTZC_TZIC1_FCR2_USB_Msk GTZC_CFGR2_USB_Msk #define GTZC_TZIC1_FCR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos #define GTZC_TZIC1_FCR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk #define GTZC_TZIC1_FCR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos #define GTZC_TZIC1_FCR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk #define GTZC_TZIC1_FCR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos #define GTZC_TZIC1_FCR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk /****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ #define GTZC_TZIC1_FCR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos #define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk #define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos #define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk #define GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos #define GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk #define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos #define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk #define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos #define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk #define GTZC_TZIC1_FCR3_ADC_Pos GTZC_CFGR3_ADC_Pos #define GTZC_TZIC1_FCR3_ADC_Msk GTZC_CFGR3_ADC_Msk #define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos #define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk #define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos #define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk #define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos #define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk #define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos #define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk #define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos #define GTZC_TZIC1_FCR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk #define GTZC_TZIC1_FCR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos #define GTZC_TZIC1_FCR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk #define GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos #define GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk /******************* Bits definition for GTZC_TZIC_FCR4 register ***************/ #define GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos #define GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk #define GTZC_TZIC1_FCR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos #define GTZC_TZIC1_FCR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk #define GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos #define GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk #define GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos #define GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk #define GTZC_TZIC1_FCR4_SBS_Pos GTZC_CFGR4_SBS_Pos #define GTZC_TZIC1_FCR4_SBS_Msk GTZC_CFGR4_SBS_Msk #define GTZC_TZIC1_FCR4_RTC_Pos GTZC_CFGR4_RTC_Pos #define GTZC_TZIC1_FCR4_RTC_Msk GTZC_CFGR4_RTC_Msk #define GTZC_TZIC1_FCR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos #define GTZC_TZIC1_FCR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk #define GTZC_TZIC1_FCR4_PWR_Pos GTZC_CFGR4_PWR_Pos #define GTZC_TZIC1_FCR4_PWR_Msk GTZC_CFGR4_PWR_Msk #define GTZC_TZIC1_FCR4_RCC_Pos GTZC_CFGR4_RCC_Pos #define GTZC_TZIC1_FCR4_RCC_Msk GTZC_CFGR4_RCC_Msk #define GTZC_TZIC1_FCR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos #define GTZC_TZIC1_FCR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk #define GTZC_TZIC1_FCR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos #define GTZC_TZIC1_FCR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk #define GTZC_TZIC1_FCR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos #define GTZC_TZIC1_FCR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk #define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos #define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk #define GTZC_TZIC1_FCR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos #define GTZC_TZIC1_FCR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk #define GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos #define GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk #define GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos #define GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk #define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos #define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk #define GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos #define GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk #define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos #define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk #define GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos #define GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk #define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos #define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk /******************* Bits definition for GTZC_MPCBB_CR register *****************/ #define GTZC_MPCBB_CR_GLOCK_Pos (0U) #define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ #define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) #define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ #define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) #define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ /******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ /******************************************************************************/ /* */ /* UCPD */ /* */ /******************************************************************************/ /******************** Bits definition for UCPD_CFG1 register *******************/ #define UCPD_CFG1_HBITCLKDIV_Pos (0U) #define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ #define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ #define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ #define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ #define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ #define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ #define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ #define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ #define UCPD_CFG1_IFRGAP_Pos (6U) #define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ #define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ #define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ #define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ #define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ #define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ #define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ #define UCPD_CFG1_TRANSWIN_Pos (11U) #define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ #define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ #define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ #define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ #define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ #define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ #define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ #define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) #define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ #define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ #define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ #define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ #define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ #define UCPD_CFG1_RXORDSETEN_Pos (20U) #define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */ #define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ #define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */ #define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */ #define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */ #define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */ #define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */ #define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */ #define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */ #define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */ #define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */ #define UCPD_CFG1_TXDMAEN_Pos (29U) #define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ #define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ #define UCPD_CFG1_RXDMAEN_Pos (30U) #define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ #define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ #define UCPD_CFG1_UCPDEN_Pos (31U) #define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ #define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ /******************** Bits definition for UCPD_CFG2 register *******************/ #define UCPD_CFG2_RXFILTDIS_Pos (0U) #define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ #define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ #define UCPD_CFG2_RXFILT2N3_Pos (1U) #define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ #define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ #define UCPD_CFG2_FORCECLK_Pos (2U) #define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ #define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ #define UCPD_CFG2_WUPEN_Pos (3U) #define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ #define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ #define UCPD_CFG2_RXAFILTEN_Pos (8U) #define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ #define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */ /******************** Bits definition for UCPD_CFG3 register *******************/ #define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) #define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ #define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ #define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) #define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ #define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ #define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) #define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ #define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ #define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) #define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ #define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ /******************** Bits definition for UCPD_CR register ********************/ #define UCPD_CR_TXMODE_Pos (0U) #define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ #define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ #define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ #define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ #define UCPD_CR_TXSEND_Pos (2U) #define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ #define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ #define UCPD_CR_TXHRST_Pos (3U) #define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ #define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ #define UCPD_CR_RXMODE_Pos (4U) #define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ #define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ #define UCPD_CR_PHYRXEN_Pos (5U) #define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ #define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ #define UCPD_CR_PHYCCSEL_Pos (6U) #define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ #define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ #define UCPD_CR_ANASUBMODE_Pos (7U) #define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ #define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ #define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ #define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ #define UCPD_CR_ANAMODE_Pos (9U) #define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ #define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ #define UCPD_CR_CCENABLE_Pos (10U) #define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ #define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ #define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ #define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ #define UCPD_CR_USEEXTPHY_Pos (12U) #define UCPD_CR_USEEXTPHY_Msk (0x1UL << UCPD_CR_USEEXTPHY_Pos) /*!< 0x00001000 */ #define UCPD_CR_USEEXTPHY UCPD_CR_USEEXTPHY_Msk /*!< Controls enable of USB Power Delivery transmitter */ #define UCPD_CR_CC2VCONNEN_Pos (13U) #define UCPD_CR_CC2VCONNEN_Msk (0x1UL << UCPD_CR_CC2VCONNEN_Pos) /*!< 0x00002000 */ #define UCPD_CR_CC2VCONNEN UCPD_CR_CC2VCONNEN_Msk /*!< VCONN enable for CC2 */ #define UCPD_CR_CC1VCONNEN_Pos (14U) #define UCPD_CR_CC1VCONNEN_Msk (0x1UL << UCPD_CR_CC1VCONNEN_Pos) /*!< 0x00004000 */ #define UCPD_CR_CC1VCONNEN UCPD_CR_CC1VCONNEN_Msk /*!< VCONN enable for CC1 */ #define UCPD_CR_DBATEN_Pos (15U) #define UCPD_CR_DBATEN_Msk (0x1UL << UCPD_CR_DBATEN_Pos) /*!< 0x00008000 */ #define UCPD_CR_DBATEN UCPD_CR_DBATEN_Msk /*!< Enable dead battery behavior (Active High) */ #define UCPD_CR_FRSRXEN_Pos (16U) #define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ #define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ #define UCPD_CR_FRSTX_Pos (17U) #define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ #define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ #define UCPD_CR_RDCH_Pos (18U) #define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ #define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ #define UCPD_CR_RPUSBABSENT_Pos (19U) #define UCPD_CR_RPUSBABSENT_Msk (0x1UL << UCPD_CR_RPUSBABSENT_Pos) /*!< 0x00080000 */ #define UCPD_CR_RPUSBABSENT UCPD_CR_RPUSBABSENT_Msk /*!< */ #define UCPD_CR_CC1TCDIS_Pos (20U) #define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ #define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ #define UCPD_CR_CC2TCDIS_Pos (21U) #define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ #define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ /******************** Bits definition for UCPD_IMR register *******************/ #define UCPD_IMR_TXISIE_Pos (0U) #define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ #define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ #define UCPD_IMR_TXMSGDISCIE_Pos (1U) #define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ #define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ #define UCPD_IMR_TXMSGSENTIE_Pos (2U) #define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ #define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ #define UCPD_IMR_TXMSGABTIE_Pos (3U) #define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ #define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ #define UCPD_IMR_HRSTDISCIE_Pos (4U) #define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ #define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ #define UCPD_IMR_HRSTSENTIE_Pos (5U) #define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ #define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ #define UCPD_IMR_TXUNDIE_Pos (6U) #define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ #define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ #define UCPD_IMR_RXNEIE_Pos (8U) #define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ #define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ #define UCPD_IMR_RXORDDETIE_Pos (9U) #define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ #define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ #define UCPD_IMR_RXHRSTDETIE_Pos (10U) #define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ #define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ #define UCPD_IMR_RXOVRIE_Pos (11U) #define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ #define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ #define UCPD_IMR_RXMSGENDIE_Pos (12U) #define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ #define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ #define UCPD_IMR_TYPECEVT1IE_Pos (14U) #define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ #define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ #define UCPD_IMR_TYPECEVT2IE_Pos (15U) #define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ #define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ #define UCPD_IMR_FRSEVTIE_Pos (20U) #define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ /******************** Bits definition for UCPD_SR register ********************/ #define UCPD_SR_TXIS_Pos (0U) #define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ #define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ #define UCPD_SR_TXMSGDISC_Pos (1U) #define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ #define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ #define UCPD_SR_TXMSGSENT_Pos (2U) #define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ #define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ #define UCPD_SR_TXMSGABT_Pos (3U) #define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ #define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ #define UCPD_SR_HRSTDISC_Pos (4U) #define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ #define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ #define UCPD_SR_HRSTSENT_Pos (5U) #define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ #define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ #define UCPD_SR_TXUND_Pos (6U) #define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ #define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ #define UCPD_SR_RXNE_Pos (8U) #define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ #define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ #define UCPD_SR_RXORDDET_Pos (9U) #define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ #define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ #define UCPD_SR_RXHRSTDET_Pos (10U) #define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ #define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ #define UCPD_SR_RXOVR_Pos (11U) #define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ #define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ #define UCPD_SR_RXMSGEND_Pos (12U) #define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ #define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ #define UCPD_SR_RXERR_Pos (13U) #define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ #define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ #define UCPD_SR_TYPECEVT1_Pos (14U) #define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ #define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ #define UCPD_SR_TYPECEVT2_Pos (15U) #define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ #define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ #define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) #define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */ #define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ #define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */ #define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */ #define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) #define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */ #define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!>2) /*!< Input modulus number of bits */ #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Compute Montgomery parameter output data */ #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ /* Compute modular exponentiation input data */ #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ #define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ #define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ #define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ /* Compute modular exponentiation output data */ #define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ #define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ /* Compute ECC scalar multiplication input data */ #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ /* Compute ECC scalar multiplication output data */ #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ #define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ /* Point check input data */ #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ #define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ /* Point check output data */ #define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ /* ECDSA signature input data */ #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ #define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ /* ECDSA signature output data */ #define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ /* ECDSA verification input data */ #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ #define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ #define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ /* ECDSA verification output data */ #define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* RSA CRT exponentiation input data */ #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ /* RSA CRT exponentiation output data */ #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular reduction input data */ #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ #define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ #define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Modular reduction output data */ #define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic addition input data */ #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic addition output data */ #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic subtraction input data */ #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic subtraction output data */ #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Arithmetic multiplication input data */ #define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Arithmetic multiplication output data */ #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Comparison input data */ #define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Comparison output data */ #define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular addition input data */ #define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ /* Modular addition output data */ #define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular inversion input data */ #define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ /* Modular inversion output data */ #define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Modular subtraction input data */ #define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ /* Modular subtraction output data */ #define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Montgomery multiplication input data */ #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ /* Montgomery multiplication output data */ #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ /* Generic Arithmetic input data */ #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ /* Generic Arithmetic output data */ #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ /* Compute ECC complete addition input data */ #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ #define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ /* Compute ECC complete addition output data */ #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ /* Compute ECC double base ladder input data */ #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ /* Compute ECC double base ladder output data */ #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ /* Compute ECC projective to affine conversion input data */ #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ /* Compute ECC projective to affine conversion output data */ #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ /** @addtogroup STM32H5xx_Peripheral_Exported_macros * @{ */ /******************************* ADC Instances ********************************/ #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ ((INSTANCE) == ADC1_S)|| \ ((INSTANCE) == ADC2_NS)|| \ ((INSTANCE) == ADC2_S)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ ((INSTANCE) == ADC1_S)) #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ ((INSTANCE) == ADC12_COMMON_S)) /******************************* PKA Instances ********************************/ #define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) /******************************* CRC Instances ********************************/ #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) /******************************* DAC Instances ********************************/ #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) /******************************* DCACHE Instances *****************************/ #define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) /******************************* DELAYBLOCK Instances *******************************/ #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ ((INSTANCE) == DLYB_SDMMC1_S) || \ ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ ((INSTANCE) == DLYB_OCTOSPI1_S )) /******************************** DMA Instances *******************************/ #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) #define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) #define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) #define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) /****************************** RAMCFG Instances ********************************/ #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) /***************************** RAMCFG ECC Instances *****************************/ #define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) /************************ RAMCFG Write Protection Instances *********************/ #define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) /******************************* GPIO Instances *******************************/ #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S)) /******************************* DCMI Instances *******************************/ #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) /******************************* PSSI Instances *******************************/ #define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) /******************************* DTS Instances *******************************/ #define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) /******************************* GPIO AF Instances ****************************/ /* On H5, all GPIO Bank support AF */ #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) /**************************** GPIO Lock Instances *****************************/ /* On H5, all GPIO Bank support the Lock mechanism */ #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) /******************************** I2C Instances *******************************/ #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) /****************** I2C Instances : wakeup capability from stop modes *********/ #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) /******************************** I3C Instances *******************************/ #define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \ ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S)) /******************************* OSPI Instances *******************************/ #define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) /******************************* RNG Instances ********************************/ #define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) /****************************** RTC Instances *********************************/ #define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) /****************************** SDMMC Instances *******************************/ #define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) /****************************** FDCAN Instances *******************************/ #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) /****************************** SMBUS Instances *******************************/ #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) #define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) /****************** LPTIM Instances : All supported instances *****************/ #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) /****************** LPTIM Instances : DMA supported instances *****************/ #define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) /************* LPTIM Instances : at least 1 capture/compare channel ***********/ #define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) /************* LPTIM Instances : at least 2 capture/compare channel ***********/ #define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) /****************** LPTIM Instances : supporting encoder interface **************/ #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) /****************** LPTIM Instances : supporting Input Capture **************/ #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) /****************** TIM Instances : All supported instances *******************/ #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting 32 bits counter ****************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /************** TIM Instances : supporting Break source selection *************/ #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting 2 break inputs *****************/ #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /************* TIM Instances : at least 1 capture/compare channel *************/ #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /************ TIM Instances : at least 2 capture/compare channels *************/ #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /************ TIM Instances : at least 3 capture/compare channels *************/ #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /************ TIM Instances : at least 4 capture/compare channels *************/ #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : at least 5 capture/compare channels *******/ #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : at least 6 capture/compare channels *******/ #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /******************** TIM Instances : DMA burst feature ***********************/ #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /******************* TIM Instances : output(s) available **********************/ #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4) || \ ((CHANNEL) == TIM_CHANNEL_5) || \ ((CHANNEL) == TIM_CHANNEL_6))) \ || \ ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4) || \ ((CHANNEL) == TIM_CHANNEL_5) || \ ((CHANNEL) == TIM_CHANNEL_6))) \ || \ ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2))) \ || \ ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2)))) /****************** TIM Instances : supporting complementary output(s) ********/ #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ ((CHANNEL) == TIM_CHANNEL_1))) /****************** TIM Instances : supporting clock division *****************/ #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : supporting commutation event generation ***/ #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting counting mode selection ********/ #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : supporting encoder interface **************/ #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : supporting Hall sensor interface **********/ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /**************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /************* TIM Instances : supporting ETR source selection ***************/ #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : supporting repetition counter *************/ #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /******************* TIM Instances : Timer input XOR function *****************/ #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /******************* TIM Instances : Timer input selection ********************/ #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) /****************** TIM Instances : Advanced timer instances *******************/ #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) /****************** TIM Instances : supporting synchronization ****************/ #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \ ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) /******************** UART Instances : Asynchronous mode **********************/ #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) /*********************** UART Instances : FIFO mode ***************************/ #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) /*********************** UART Instances : SPI Slave mode **********************/ #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) /******************************** I2S Instances *******************************/ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2) || \ ((INSTANCE) == SPI3)) /****************** UART Instances : Auto Baud Rate detection ****************/ #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) /****************** UART Instances : Driver Enable *****************/ #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) /******************** UART Instances : Half-Duplex mode **********************/ #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) /****************** UART Instances : Hardware Flow control ********************/ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) /******************** UART Instances : LIN mode **********************/ #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) /******************** UART Instances : Wake-up from Stop mode **********************/ #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) /*********************** UART Instances : IRDA mode ***************************/ #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) /********************* USART Instances : Smard card mode ***********************/ #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) /******************** LPUART Instance *****************************************/ #define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) /******************** CEC Instance *****************************************/ #define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) /****************************** WWDG Instances ********************************/ #define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) /****************************** UCPD Instances ********************************/ #define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) /******************************* USB DRD FS HCD Instances *************************/ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) /******************************* USB DRD FS PCD Instances *************************/ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) /** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ /** @} */ /* End of group STM32H523xx */ /** @} */ /* End of group ST */ #ifdef __cplusplus } #endif #endif /* STM32H523xx_H */