Lines Matching refs:Timing
380 FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
388 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
389 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Timing_Init()
390 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Timing_Init()
391 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Timing_Init()
392 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); in FSMC_NORSRAM_Timing_Init()
393 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); in FSMC_NORSRAM_Timing_Init()
394 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Timing_Init()
398 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
399 … ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) | in FSMC_NORSRAM_Timing_Init()
400 … ((Timing->DataSetupTime) << FSMC_BTR1_DATAST_Pos) | in FSMC_NORSRAM_Timing_Init()
401 … ((Timing->BusTurnAroundDuration) << FSMC_BTR1_BUSTURN_Pos) | in FSMC_NORSRAM_Timing_Init()
402 … (((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos) | in FSMC_NORSRAM_Timing_Init()
403 … (((Timing->DataLatency) - 2U) << FSMC_BTR1_DATLAT_Pos) | in FSMC_NORSRAM_Timing_Init()
404 (Timing->AccessMode))); in FSMC_NORSRAM_Timing_Init()
411 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos); in FSMC_NORSRAM_Timing_Init()
432 … FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, in FSMC_NORSRAM_Extended_Timing_Init() argument
443 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Extended_Timing_Init()
444 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Extended_Timing_Init()
445 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Extended_Timing_Init()
446 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Extended_Timing_Init()
447 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Extended_Timing_Init()
451 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Extended_Timing_Init()
452 … ((Timing->AddressHoldTime) << FSMC_BWTR1_ADDHLD_Pos) | in FSMC_NORSRAM_Extended_Timing_Init()
453 … ((Timing->DataSetupTime) << FSMC_BWTR1_DATAST_Pos) | in FSMC_NORSRAM_Extended_Timing_Init()
454 … Timing->AccessMode | in FSMC_NORSRAM_Extended_Timing_Init()
455 … ((Timing->BusTurnAroundDuration) << FSMC_BWTR1_BUSTURN_Pos))); in FSMC_NORSRAM_Extended_Timing_Init()
627 … FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NAND_CommonSpace_Timing_Init() argument
631 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_NAND_CommonSpace_Timing_Init()
632 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_NAND_CommonSpace_Timing_Init()
633 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_NAND_CommonSpace_Timing_Init()
634 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_NAND_CommonSpace_Timing_Init()
641 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime … in FSMC_NAND_CommonSpace_Timing_Init()
642 … ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) | in FSMC_NAND_CommonSpace_Timing_Init()
643 … ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) | in FSMC_NAND_CommonSpace_Timing_Init()
644 … ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos))); in FSMC_NAND_CommonSpace_Timing_Init()
649 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime … in FSMC_NAND_CommonSpace_Timing_Init()
650 … ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) | in FSMC_NAND_CommonSpace_Timing_Init()
651 … ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) | in FSMC_NAND_CommonSpace_Timing_Init()
652 … ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos))); in FSMC_NAND_CommonSpace_Timing_Init()
667 … FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NAND_AttributeSpace_Timing_Init() argument
671 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_NAND_AttributeSpace_Timing_Init()
672 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_NAND_AttributeSpace_Timing_Init()
673 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_NAND_AttributeSpace_Timing_Init()
674 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_NAND_AttributeSpace_Timing_Init()
681 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime … in FSMC_NAND_AttributeSpace_Timing_Init()
682 … ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()
683 … ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()
684 … ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos))); in FSMC_NAND_AttributeSpace_Timing_Init()
689 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime … in FSMC_NAND_AttributeSpace_Timing_Init()
690 … ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()
691 … ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) | in FSMC_NAND_AttributeSpace_Timing_Init()
692 … ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos))); in FSMC_NAND_AttributeSpace_Timing_Init()
941 FSMC_NAND_PCC_TimingTypeDef *Timing) in FSMC_PCCARD_CommonSpace_Timing_Init() argument
946 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_PCCARD_CommonSpace_Timing_Init()
947 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_PCCARD_CommonSpace_Timing_Init()
948 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_PCCARD_CommonSpace_Timing_Init()
949 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_PCCARD_CommonSpace_Timing_Init()
954 (Timing->SetupTime | in FSMC_PCCARD_CommonSpace_Timing_Init()
955 ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos) | in FSMC_PCCARD_CommonSpace_Timing_Init()
956 ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos) | in FSMC_PCCARD_CommonSpace_Timing_Init()
957 ((Timing->HiZSetupTime) << FSMC_PMEM4_MEMHIZ4_Pos))); in FSMC_PCCARD_CommonSpace_Timing_Init()
970 … FSMC_NAND_PCC_TimingTypeDef *Timing) in FSMC_PCCARD_AttributeSpace_Timing_Init() argument
975 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_PCCARD_AttributeSpace_Timing_Init()
976 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_PCCARD_AttributeSpace_Timing_Init()
977 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_PCCARD_AttributeSpace_Timing_Init()
978 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_PCCARD_AttributeSpace_Timing_Init()
983 (Timing->SetupTime | in FSMC_PCCARD_AttributeSpace_Timing_Init()
984 ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos) | in FSMC_PCCARD_AttributeSpace_Timing_Init()
985 ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos) | in FSMC_PCCARD_AttributeSpace_Timing_Init()
986 ((Timing->HiZSetupTime) << FSMC_PATT4_ATTHIZ4_Pos))); in FSMC_PCCARD_AttributeSpace_Timing_Init()
999 FSMC_NAND_PCC_TimingTypeDef *Timing) in FSMC_PCCARD_IOSpace_Timing_Init() argument
1004 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); in FSMC_PCCARD_IOSpace_Timing_Init()
1005 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); in FSMC_PCCARD_IOSpace_Timing_Init()
1006 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); in FSMC_PCCARD_IOSpace_Timing_Init()
1007 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); in FSMC_PCCARD_IOSpace_Timing_Init()
1012 (Timing->SetupTime | in FSMC_PCCARD_IOSpace_Timing_Init()
1013 (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | in FSMC_PCCARD_IOSpace_Timing_Init()
1014 (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | in FSMC_PCCARD_IOSpace_Timing_Init()
1015 (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos))); in FSMC_PCCARD_IOSpace_Timing_Init()