220 HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_Init()  argument
228   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_Init()
253   __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FSMC_NORSRAM_Init()
314   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FSMC_NORSRAM_Init()
320     MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock);  in FSMC_NORSRAM_Init()
328     SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));  in FSMC_NORSRAM_Init()
342 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_DeInit()  argument
346   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_DeInit()
351   __FSMC_NORSRAM_DISABLE(Device, Bank);  in FSMC_NORSRAM_DeInit()
357     Device->BTCR[Bank] = 0x000030DBU;  in FSMC_NORSRAM_DeInit()
362     Device->BTCR[Bank] = 0x000030D2U;  in FSMC_NORSRAM_DeInit()
365   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FSMC_NORSRAM_DeInit()
379 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,  in FSMC_NORSRAM_Timing_Init()  argument
387   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_Timing_Init()
398 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                     …  in FSMC_NORSRAM_Timing_Init()
408   if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))  in FSMC_NORSRAM_Timing_Init()
410     tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos));  in FSMC_NORSRAM_Timing_Init()
412     MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr);  in FSMC_NORSRAM_Timing_Init()
431 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,  in FSMC_NORSRAM_Extended_Timing_Init()  argument
442     assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));  in FSMC_NORSRAM_Extended_Timing_Init()
451 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FSMC_NORSRAM_Extended_Timing_Init()
459     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FSMC_NORSRAM_Extended_Timing_Init()
489 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Enable()  argument
492   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_WriteOperation_Enable()
496   SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Enable()
507 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FSMC_NORSRAM_WriteOperation_Disable()  argument
510   assert_param(IS_FSMC_NORSRAM_DEVICE(Device));  in FSMC_NORSRAM_WriteOperation_Disable()
514   CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);  in FSMC_NORSRAM_WriteOperation_Disable()
579 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)  in FSMC_NAND_Init()  argument
582   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_Init()
595 … MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                      |  in FSMC_NAND_Init()
606 … MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                      |  in FSMC_NAND_Init()
626 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,  in FSMC_NAND_CommonSpace_Timing_Init()  argument
630   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_CommonSpace_Timing_Init()
641 …MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_CommonSpace_Timing_Init()
649 …MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_CommonSpace_Timing_Init()
666 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,  in FSMC_NAND_AttributeSpace_Timing_Init()  argument
670   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_AttributeSpace_Timing_Init()
681 …MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_AttributeSpace_Timing_Init()
689 …MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                                     …  in FSMC_NAND_AttributeSpace_Timing_Init()
704 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_DeInit()  argument
707   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_DeInit()
711   __FSMC_NAND_DISABLE(Device, Bank);  in FSMC_NAND_DeInit()
717     WRITE_REG(Device->PCR2,  0x00000018U);  in FSMC_NAND_DeInit()
718     WRITE_REG(Device->SR2,   0x00000040U);  in FSMC_NAND_DeInit()
719     WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
720     WRITE_REG(Device->PATT2, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
726     WRITE_REG(Device->PCR3,  0x00000018U);  in FSMC_NAND_DeInit()
727     WRITE_REG(Device->SR3,   0x00000040U);  in FSMC_NAND_DeInit()
728     WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
729     WRITE_REG(Device->PATT3, 0xFCFCFCFCU);  in FSMC_NAND_DeInit()
761 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Enable()  argument
764   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_ECC_Enable()
770     SET_BIT(Device->PCR2, FSMC_PCR2_ECCEN);  in FSMC_NAND_ECC_Enable()
774     SET_BIT(Device->PCR3, FSMC_PCR2_ECCEN);  in FSMC_NAND_ECC_Enable()
787 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)  in FSMC_NAND_ECC_Disable()  argument
790   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_ECC_Disable()
796     CLEAR_BIT(Device->PCR2, FSMC_PCR2_ECCEN);  in FSMC_NAND_ECC_Disable()
800     CLEAR_BIT(Device->PCR3, FSMC_PCR2_ECCEN);  in FSMC_NAND_ECC_Disable()
814 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FSMC_NAND_GetECC()  argument
820   assert_param(IS_FSMC_NAND_DEVICE(Device));  in FSMC_NAND_GetECC()
827   while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)  in FSMC_NAND_GetECC()
842     *ECCval = (uint32_t)Device->ECCR2;  in FSMC_NAND_GetECC()
847     *ECCval = (uint32_t)Device->ECCR3;  in FSMC_NAND_GetECC()
907 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)  in FSMC_PCCARD_Init()  argument
910   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_Init()
918   MODIFY_REG(Device->PCR4,  in FSMC_PCCARD_Init()
940 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_CommonSpace_Timing_Init()  argument
944   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_CommonSpace_Timing_Init()
953   MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,  in FSMC_PCCARD_CommonSpace_Timing_Init()
969 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_AttributeSpace_Timing_Init()  argument
973   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_AttributeSpace_Timing_Init()
982   MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,  in FSMC_PCCARD_AttributeSpace_Timing_Init()
998 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,  in FSMC_PCCARD_IOSpace_Timing_Init()  argument
1002   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_IOSpace_Timing_Init()
1011   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,  in FSMC_PCCARD_IOSpace_Timing_Init()
1025 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)  in FSMC_PCCARD_DeInit()  argument
1028   assert_param(IS_FSMC_PCCARD_DEVICE(Device));  in FSMC_PCCARD_DeInit()
1031   __FSMC_PCCARD_DISABLE(Device);  in FSMC_PCCARD_DeInit()
1034   Device->PCR4    = 0x00000018U;  in FSMC_PCCARD_DeInit()
1035   Device->SR4     = 0x00000040U;  in FSMC_PCCARD_DeInit()
1036   Device->PMEM4   = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()
1037   Device->PATT4   = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()
1038   Device->PIO4    = 0xFCFCFCFCU;  in FSMC_PCCARD_DeInit()