Lines Matching refs:BTCR
314 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FSMC_NORSRAM_Init()
320 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock); in FSMC_NORSRAM_Init()
328 SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FSMC_NORSRAM_Init()
357 Device->BTCR[Bank] = 0x000030DBU; in FSMC_NORSRAM_DeInit()
362 Device->BTCR[Bank] = 0x000030D2U; in FSMC_NORSRAM_DeInit()
365 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FSMC_NORSRAM_DeInit()
398 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FSMC_NORSRAM_Timing_Init()
408 if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) in FSMC_NORSRAM_Timing_Init()
410 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos)); in FSMC_NORSRAM_Timing_Init()
412 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr); in FSMC_NORSRAM_Timing_Init()
496 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Enable()
514 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Disable()