Lines Matching full:with
14 * If no LICENSE file comes with this software, it is provided AS-IS.
117 … compatibility with some ADC on other STM32 series
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
129 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
147 … compatibility with some ADC on other STM32 series
151 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
159 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
364 … | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
375 with which VrefInt has been calibrated in production
391 … with which temperature sensor has been calibrated in production (tolerance +-10 mV) (unit: mV). */
447 (for devices with several ADC instances).
478 * (setting possible with ADC enabled without conversion on going,
479 * ADC enabled with conversion on going, ...)
480 * Each feature can be updated afterwards with a unitary function
481 * and potentially with ADC in a different state than disabled,
509 * (functions with prefix "REG").
516 * (setting possible with ADC enabled without conversion on going,
517 * ADC enabled with conversion on going, ...)
518 * Each feature can be updated afterwards with a unitary function
519 * and potentially with ADC in a different state than disabled,
530 … with some ADC on other STM32 series having this setting set by HW
579 * (functions with prefix "INJ").
586 * (setting possible with ADC enabled without conversion on going,
587 * ADC enabled with conversion on going, ...)
588 * Each feature can be updated afterwards with a unitary function
589 * and potentially with ADC in a different state than disabled,
600 … compatibility with some ADC on other STM32 series having this
641 * @brief Flags defines which can be used with LL_ADC_ReadReg function
709 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
733 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
736 /* List of ADC registers intended to be used (most commonly) with */
740 … (corresponding to register DR) to be used with ADC configured in independent
746 … (corresponding to register CDR) to be used with ADC configured in multimode
747 (available on STM32 devices with several ADC instances).
761 AHB clock with prescaler division by 2 */
763 AHB clock with prescaler division by 4 */
766 …DC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
768 …DC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
770 …DC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
772 …DC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
774 …DC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
776 …DC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
779 … | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
781 …DC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
783 …DC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
785 …DC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
788 … | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
840 … See description with function @ref LL_ADC_SetLowPowerMode(). */
1051 … This ADC mode is intended to be used with DMA mode non-circular. */
1055 … This ADC mode is intended to be used with DMA mode circular. */
1081 … with selection sampling time 2.5 ADC clock cycles, whatever channels mapped
1105 with 2 ranks in the sequence */
1107 with 3 ranks in the sequence */
1109 with 4 ranks in the sequence */
1111 with 5 ranks in the sequence */
1113 with 6 ranks in the sequence */
1115 with 7 ranks in the sequence */
1118 with 8 ranks in the sequence */
1120 with 9 ranks in the sequence */
1122 with 10 ranks in the sequence */
1124 with 11 ranks in the sequence */
1127 with 12 ranks in the sequence */
1129 with 13 ranks in the sequence */
1132 with 14 ranks in the sequence */
1135 with 15 ranks in the sequence */
1138 … with 16 ranks in the sequence */
1149 … discontinuous mode enable with sequence interruption every rank */
1151 … discontinuous mode enabled with sequence interruption every 2 ranks */
1153 … discontinuous mode enable with sequence interruption every 3 ranks */
1156 … discontinuous mode enable with sequence interruption every 4 ranks */
1158 … discontinuous mode enable with sequence interruption every 5 ranks */
1161 … discontinuous mode enable with sequence interruption every 6 ranks */
1164 … discontinuous mode enable with sequence interruption every 7 ranks */
1167 … discontinuous mode enable with sequence interruption every 8 ranks */
1306 … regular. Setting compliant only with group injected trigger source set to
1335 with 2 ranks in the sequence */
1337 with 3 ranks in the sequence */
1339 with 4 ranks in the sequence */
1350 enable with sequence interruption every rank */
1825 … alternate trigger. Works only with external triggers (not SW start) */
1841 with its individual DMA transfer settings */
1846 … is reached. This ADC mode is intended to be used with DMA mode
1852 … is reached. This ADC mode is intended to be used with DMA mode
1858 … This ADC mode is intended to be used with DMA mode circular.
1865 … This ADC mode is intended to be used with DMA mode circular.
2040 * number is returned, either defined with number
2041 * or with bitfield (only one bit must be set).
2069 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2119 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2124 * comparison with internal channel parameter to be done
2157 * number in ADC registers. The differentiation is made only with
2186 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2236 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2274 * number in ADC registers. The differentiation is made only with
2305 * define a single channel to monitor with analog watchdog
2307 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2339 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2344 * comparison with internal channel parameter to be done
2445 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2447 * Example, with a ADC resolution of 8 bits, to set the value of
2468 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2469 * Example, with a ADC resolution of 8 bits, to get the value of
2489 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2503 * @brief Helper macro to set the ADC calibration value with both single ended
2505 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2521 * or ADC slave from raw value with both ADC conversion data concatenated.
2524 * In this case the transferred data need to processed with this macro
2541 * @note In case of device with multimode available and a mix of
2542 * ADC instances compliant and not compliant with multimode feature,
2543 * ADC instances not compliant with multimode feature are
2563 * - Multimode (for devices with several ADC instances)
2582 * @note This check is required by functions with setting conditioned to
2586 * @note On devices with only 1 ADC common instance, parameter of this macro
2588 * with devices featuring several ADC common instances).
2683 * On devices with small package, the pin Vref+ is not present
2717 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2780 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2787 * of the current device has characteristics in line with
2860 * intended to be used (most commonly) with DMA transfer.
2864 * @note This macro is intended to be used with LL DMA driver, refer to
2872 * @note For devices with several ADC: in multimode, some devices
2884 * (1) Available on devices with several ADC instances.
2934 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3015 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3057 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3087 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3139 * or differential (for devices with differential mode available).
3143 * @note For devices with differential mode available:
3179 * or differential (for devices with differential mode available).
3182 * @note For devices with differential mode available:
3195 /* Retrieve bits with position in register depending on parameter */ in LL_ADC_GetCalibrationFactor()
3197 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ in LL_ADC_GetCalibrationFactor()
3296 * - It is not recommended to use with interruption or DMA
3302 * - Do use with polling: 1. Start conversion,
3307 * @note With ADC low power mode "auto wait", the ADC conversion data read
3346 * - It is not recommended to use with interruption or DMA
3352 * - Do use with polling: 1. Start conversion,
3357 * @note With ADC low power mode "auto wait", the ADC conversion data read
3388 * with the lowest value is considered for the subtraction.
3440 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
3464 * with parts of literals LL_ADC_CHANNEL_x or using
3469 * process the returned value with the helper macro
3510 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
3515 * comparison with internal channel parameter to be done
3659 * (default setting for compatibility with some ADC on other
3740 /* to match with triggers literals definition. */ in LL_ADC_REG_GetTriggerSource()
3801 * - For devices with sequencer fully configurable
3811 * - For devices with sequencer not fully configurable
3860 * - For devices with sequencer fully configurable
3870 * - For devices with sequencer not fully configurable
4047 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4054 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_REG_SetSequencerRanks()
4056 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_REG_SetSequencerRanks()
4080 * with parts of literals LL_ADC_CHANNEL_x or using
4085 * process the returned value with the helper macro
4148 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4153 * comparison with internal channel parameter to be done
4216 * This ADC mode is intended to be used with DMA mode non-circular.
4220 * This ADC mode is intended to be used with DMA mode circular.
4226 * @note For devices with several ADC instances: ADC multimode DMA
4256 * This ADC mode is intended to be used with DMA mode non-circular.
4260 * This ADC mode is intended to be used with DMA mode circular.
4266 * @note For devices with several ADC instances: ADC multimode DMA
4323 * @note Compatibility with devices without feature overrun:
4327 * Therefore, for compatibility with all devices, parameter
4373 * (default setting for compatibility with some ADC on other
4381 * ADC must not be disabled. Can be enabled with or without conversion
4454 /* to match with triggers literals definition. */ in LL_ADC_INJ_GetTriggerSource()
4482 * ADC must not be disabled. Can be enabled with or without conversion
4522 * ADC must not be disabled. Can be enabled with or without conversion
4605 * ADC must not be disabled. Can be enabled with or without conversion
4644 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4651 /* Set bits with content of parameter "Channel" with bits position */ in LL_ADC_INJ_SetSequencerRanks()
4653 /* Parameters "Rank" and "Channel" are used with masks because containing */ in LL_ADC_INJ_SetSequencerRanks()
4671 * with parts of literals LL_ADC_CHANNEL_x or using
4676 * process the returned value with the helper macro
4715 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4720 * comparison with internal channel parameter to be done
4736 * updated after one ADC conversion trigger and with data
4744 * ADC group injected automatic trigger is compliant only with
4867 * ADC must not be disabled. Can be enabled with or without conversion
4934 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4964 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4994 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
5024 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
5038 /* Set bits with content of parameter "Rankx_Channel" with bits position */ in LL_ADC_INJ_ConfigQueueContext()
5040 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ in LL_ADC_INJ_ConfigQueueContext()
5148 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
5168 /* Set bits with content of parameter "SamplingTime" with bits position */ in LL_ADC_SetChannelSamplingTime()
5170 /* Parameter "Channel" is used with masks because containing */ in LL_ADC_SetChannelSamplingTime()
5238 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
5386 * with analog watchdog from sequencer channel definition,
5508 /* Set bits with content of parameter "AWDChannelGroup" with bits position */ in LL_ADC_SetAnalogWDMonitChannels()
5510 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ in LL_ADC_SetAnalogWDMonitChannels()
5528 * with parts of literals LL_ADC_CHANNEL_x or using
5533 * process the returned value with the helper macro
5767 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ in LL_ADC_ConfigAnalogWDThresholds()
5770 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ in LL_ADC_ConfigAnalogWDThresholds()
5847 /* Set bits with content of parameter "AWDThresholdValue" with bits */ in LL_ADC_SetAnalogWDThresholds()
5850 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ in LL_ADC_SetAnalogWDThresholds()
5862 * threshold low or raw data with ADC thresholds high and low
5864 * @note If raw data with ADC thresholds high and low is retrieved,
6100 * or multimode (for devices with several ADC instances).
6107 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6131 * or multimode (for devices with several ADC instances).
6157 * each ADC uses its own DMA channel, with its individual
6165 * This ADC mode is intended to be used with DMA mode non-circular.
6169 * This ADC mode is intended to be used with DMA mode circular.
6179 * is a raw data with ADC master and slave concatenated.
6208 * each ADC uses its own DMA channel, with its individual
6216 * This ADC mode is intended to be used with DMA mode non-circular.
6220 * This ADC mode is intended to be used with DMA mode circular.
6230 * is a raw data with ADC master and slave concatenated.
6260 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6341 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableDeepPowerDown()
6343 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableDeepPowerDown()
6364 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_DisableDeepPowerDown()
6366 /* to not interfere with bits with HW property "rs". */ in LL_ADC_DisableDeepPowerDown()
6397 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_EnableInternalRegulator()
6399 /* to not interfere with bits with HW property "rs". */ in LL_ADC_EnableInternalRegulator()
6448 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Enable()
6450 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Enable()
6468 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_Disable()
6470 /* to not interfere with bits with HW property "rs". */ in LL_ADC_Disable()
6503 * or differential (for devices with differential mode available).
6507 * @note For devices with differential mode available:
6526 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_StartCalibration()
6528 /* to not interfere with bits with HW property "rs". */ in LL_ADC_StartCalibration()
6573 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StartConversion()
6575 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StartConversion()
6585 * ADC must be enabled with conversion on going on group regular,
6593 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_REG_StopConversion()
6595 /* to not interfere with bits with HW property "rs". */ in LL_ADC_REG_StopConversion()
6627 * with feature oversampling).
6640 * @note For devices with feature oversampling: Oversampling
6655 * @note For devices with feature oversampling: Oversampling
6670 * @note For devices with feature oversampling: Oversampling
6685 * @note For devices with feature oversampling: Oversampling
6700 * or raw data with ADC master and slave concatenated.
6701 * @note If raw data with ADC master and slave concatenated is retrieved,
6757 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StartConversion()
6759 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StartConversion()
6769 * ADC must be enabled with conversion on going on group injected,
6777 /* Note: Write register with some additional bits forced to state reset */ in LL_ADC_INJ_StopConversion()
6779 /* to not interfere with bits with HW property "rs". */ in LL_ADC_INJ_StopConversion()
6811 * with feature oversampling).
6837 * @note For devices with feature oversampling: Oversampling
6865 * @note For devices with feature oversampling: Oversampling
6893 * @note For devices with feature oversampling: Oversampling
6921 * @note For devices with feature oversampling: Oversampling