Lines Matching full:name
110 FXOSC_CLK, /* Clock name associated to xosc */
129 COREPLL_CLK, /* name */
157 PERIPHPLL_CLK, /* name */
185 DDRPLL_CLK, /* name */
213 LFAST0_PLL_CLK, /* name */
241 LFAST1_PLL_CLK, /* name */
272 P0_SYS_CLK, /* Clock name associated to selector */
273 COREPLL_DFS1_CLK, /* Name of the selected input source */
279 P0_REG_INTF_CLK, /* Clock name associated to selector */
280 COREPLL_DFS4_CLK, /* Name of the selected input source */
286 P0_PSI5_1US_CLK, /* Clock name associated to selector */
287 FIRC_CLK, /* Name of the selected input source */
293 P0_PSI5_S_TRIG0_CLK, /* Clock name associated to selector */
294 FIRC_CLK, /* Name of the selected input source */
300 P0_LIN_BAUD_CLK, /* Clock name associated to selector */
301 FIRC_CLK, /* Name of the selected input source */
307 P0_DSPI_CLK, /* Clock name associated to selector */
308 PERIPHPLL_PHI1_CLK, /* Name of the selected input source */
314 P0_FR_PE_CLK, /* Clock name associated to selector */
315 FIRC_CLK, /* Name of the selected input source */
321 P0_NANO_CLK, /* Clock name associated to selector */
322 PERIPHPLL_PHI0_CLK, /* Name of the selected input source */
328 GLB_LBIST_CLK, /* Clock name associated to selector */
329 COREPLL_DFS5_CLK, /* Name of the selected input source */
335 P0_EMIOS_LCU_CLK, /* Clock name associated to selector */
336 FIRC_CLK, /* Name of the selected input source */
342 CLKOUT0_CLK, /* Clock name associated to selector */
343 FIRC_CLK, /* Name of the selected input source */
349 P1_SYS_CLK, /* Clock name associated to selector */
350 COREPLL_DFS1_CLK, /* Name of the selected input source */
356 P1_REG_INTF_CLK, /* Clock name associated to selector */
357 COREPLL_DFS4_CLK, /* Name of the selected input source */
363 P1_DSPI_CLK, /* Clock name associated to selector */
364 PERIPHPLL_PHI1_CLK, /* Name of the selected input source */
370 P1_DSPI60_CLK, /* Clock name associated to selector */
371 PERIPHPLL_PHI2_CLK, /* Name of the selected input source */
377 P1_LIN_BAUD_CLK, /* Clock name associated to selector */
378 FIRC_CLK, /* Name of the selected input source */
384 ETH_TS_CLK, /* Clock name associated to selector */
385 FIRC_CLK, /* Name of the selected input source */
391 ETH0_TX_MII_CLK, /* Clock name associated to selector */
392 COREPLL_DFS3_CLK, /* Name of the selected input source */
398 ETH0_RX_MII_CLK, /* Clock name associated to selector */
399 ETH0_EXT_RX_CLK, /* Name of the selected input source */
405 ETH1_TX_MII_CLK, /* Clock name associated to selector */
406 COREPLL_DFS3_CLK, /* Name of the selected input source */
412 ETH1_RX_MII_CLK, /* Clock name associated to selector */
413 COREPLL_DFS3_CLK, /* Name of the selected input source */
419 CLKOUT1_CLK, /* Clock name associated to selector */
420 FIRC_CLK, /* Name of the selected input source */
426 P1_LFAST0_REF_CLK, /* Clock name associated to selector */
427 FXOSC_CLK, /* Name of the selected input source */
433 P1_LFAST1_REF_CLK, /* Clock name associated to selector */
434 FXOSC_CLK, /* Name of the selected input source */
440 P1_NETC_AXI_CLK, /* Clock name associated to selector */
441 PERIPHPLL_DFS5_CLK, /* Name of the selected input source */
447 P2_SYS_CLK, /* Clock name associated to selector */
448 COREPLL_DFS4_CLK, /* Name of the selected input source */
454 P2_REG_INTF_CLK, /* Clock name associated to selector */
455 FIRC_CLK, /* Name of the selected input source */
461 P2_DBG_ATB_CLK, /* Clock name associated to selector */
462 FIRC_CLK, /* Name of the selected input source */
468 P2_MATH_CLK, /* Clock name associated to selector */
469 COREPLL_DFS2_CLK, /* Name of the selected input source */
475 P3_SYS_CLK, /* Clock name associated to selector */
476 COREPLL_DFS1_CLK, /* Name of the selected input source */
482 P3_REG_INTF_CLK, /* Clock name associated to selector */
483 FIRC_CLK, /* Name of the selected input source */
489 P3_DBG_TS_CLK, /* Clock name associated to selector */
490 FIRC_CLK, /* Name of the selected input source */
496 P3_CAN_PE_CLK, /* Clock name associated to selector */
497 PERIPHPLL_PHI5_CLK, /* Name of the selected input source */
503 CLKOUT4_CLK, /* Clock name associated to selector */
504 FIRC_CLK, /* Name of the selected input source */
510 P4_SYS_CLK, /* Clock name associated to selector */
511 COREPLL_DFS4_CLK, /* Name of the selected input source */
517 P4_REG_INTF_CLK, /* Clock name associated to selector */
518 COREPLL_DFS1_CLK, /* Name of the selected input source */
524 P4_PSI5_1US_CLK, /* Clock name associated to selector */
525 FIRC_CLK, /* Name of the selected input source */
531 P4_PSI5_S_TRIG0_CLK, /* Clock name associated to selector */
532 FIRC_CLK, /* Name of the selected input source */
538 P4_DSPI_CLK, /* Clock name associated to selector */
539 PERIPHPLL_PHI1_CLK, /* Name of the selected input source */
545 P4_DSPI60_CLK, /* Clock name associated to selector */
546 PERIPHPLL_PHI2_CLK, /* Name of the selected input source */
552 CLKOUT2_CLK, /* Clock name associated to selector */
553 FIRC_CLK, /* Name of the selected input source */
559 P4_QSPI0_2X_CLK, /* Clock name associated to selector */
560 FIRC_CLK, /* Name of the selected input source */
566 P4_LIN_BAUD_CLK, /* Clock name associated to selector */
567 FIRC_CLK, /* Name of the selected input source */
573 P4_SDHC_CLK, /* Clock name associated to selector */
574 FIRC_CLK, /* Name of the selected input source */
580 P4_SDHC_IP_CLK, /* Clock name associated to selector */
581 FIRC_CLK, /* Name of the selected input source */
587 P4_EMIOS_LCU_CLK, /* Clock name associated to selector */
588 FIRC_CLK, /* Name of the selected input source */
594 P5_SYS_CLK, /* Clock name associated to selector */
595 COREPLL_DFS4_CLK, /* Name of the selected input source */
601 P5_REG_INTF_CLK, /* Clock name associated to selector */
602 FIRC_CLK, /* Name of the selected input source */
608 P5_LIN_BAUD_CLK, /* Clock name associated to selector */
609 FIRC_CLK, /* Name of the selected input source */
615 P5_DSPI_CLK, /* Clock name associated to selector */
616 PERIPHPLL_PHI1_CLK, /* Name of the selected input source */
622 CLKOUT3_CLK, /* Clock name associated to selector */
623 FIRC_CLK, /* Name of the selected input source */
629 P5_DIPORT_CLK, /* Clock name associated to selector */
630 PERIPHPLL_DFS1_CLK, /* Name of the selected input source */
636 DDR_CLK, /* Clock name associated to selector */
637 DDRPLL_PHI0_CLK, /* Name of the selected input source */
643 P6_REG_INTF_CLK, /* Clock name associated to selector */
644 FIRC_CLK, /* Name of the selected input source */
650 RTU0_CORE_CLK, /* Clock name associated to selector */
651 COREPLL_DFS0_CLK, /* Name of the selected input source */
657 RTU0_REG_INTF_CLK, /* Clock name associated to selector */
658 COREPLL_DFS1_CLK, /* Name of the selected input source */
664 RTU1_CORE_CLK, /* Clock name associated to selector */
665 COREPLL_DFS0_CLK, /* Name of the selected input source */
671 RTU1_REG_INTF_CLK, /* Clock name associated to selector */
672 COREPLL_DFS1_CLK, /* Name of the selected input source */
678 P0_CLKOUT_SRC_CLK, /* Clock name associated to selector */
679 FIRC_CLK, /* Name of the selected input source */
685 P1_CLKOUT_SRC_CLK, /* Clock name associated to selector */
686 P1_SYS_CLK, /* Name of the selected input source */
692 P3_CLKOUT_SRC_CLK, /* Clock name associated to selector */
693 P3_SYS_CLK, /* Name of the selected input source */
699 P4_CLKOUT_SRC_CLK, /* Clock name associated to selector */
700 P4_SYS_CLK, /* Name of the selected input source */
706 P5_CLKOUT_SRC_CLK, /* Clock name associated to selector */
707 P5_SYS_CLK, /* Name of the selected input source */
717 CLKOUT0_CLK, /* name */
727 CLKOUT1_CLK, /* name */
737 COREPLL_PHI0_CLK, /* name */
747 DDR_CLK, /* name */
757 DDRPLL_PHI0_CLK, /* name */
767 ETH_TS_CLK, /* name */
777 ETH0_REF_RMII_CLK, /* name */
787 ETH0_RX_MII_CLK, /* name */
797 ETH0_RX_RGMII_CLK, /* name */
807 ETH0_TX_MII_CLK, /* name */
817 ETH0_TX_RGMII_CLK, /* name */
827 ETH1_REF_RMII_CLK, /* name */
837 ETH1_RX_MII_CLK, /* name */
847 ETH1_RX_RGMII_CLK, /* name */
857 ETH1_TX_MII_CLK, /* name */
867 ETH1_TX_RGMII_CLK, /* name */
877 GLB_LBIST_CLK, /* name */
887 P0_CTU_PER_CLK, /* name */
897 P0_DSPI_MSC_CLK, /* name */
907 P0_FR_PE_CLK, /* name */
917 P0_GTM_CLK, /* name */
927 P0_LIN_BAUD_CLK, /* name */
937 P0_PSI5_125K_CLK, /* name */
947 P0_PSI5_189K_CLK, /* name */
957 P0_PSI5_1US_CLK, /* name */
967 P0_PSI5_S_BAUD_CLK, /* name */
977 P0_PSI5_S_TRIG0_CLK, /* name */
987 P0_PSI5_S_TRIG1_CLK, /* name */
997 P0_PSI5_S_TRIG2_CLK, /* name */
1007 P0_PSI5_S_TRIG3_CLK, /* name */
1017 P0_PSI5_S_UART_CLK, /* name */
1027 P0_PSI5_S_UTIL_CLK, /* name */
1037 P0_PSI5_S_WDOG0_CLK, /* name */
1047 P0_PSI5_S_WDOG1_CLK, /* name */
1057 P0_PSI5_S_WDOG2_CLK, /* name */
1067 P0_PSI5_S_WDOG3_CLK, /* name */
1077 P1_LFAST0_REF_CLK, /* name */
1087 P1_LFAST1_REF_CLK, /* name */
1097 P1_LIN_BAUD_CLK, /* name */
1107 P1_NETC_AXI_CLK, /* name */
1117 P1_REG_INTF_CLK, /* name */
1127 P2_REG_INTF_CLK, /* name */
1137 P3_AES_CLK, /* name */
1147 P3_CAN_PE_CLK, /* name */
1157 CLKOUT4_CLK, /* name */
1167 P3_DBG_TS_CLK, /* name */
1177 P3_REG_INTF_CLK, /* name */
1187 CLKOUT2_CLK, /* name */
1197 P4_LIN_BAUD_CLK, /* name */
1207 P4_PSI5_125K_CLK, /* name */
1217 P4_PSI5_189K_CLK, /* name */
1227 P4_PSI5_1US_CLK, /* name */
1237 P4_PSI5_S_BAUD_CLK, /* name */
1247 P4_PSI5_S_TRIG0_CLK, /* name */
1257 P4_PSI5_S_TRIG1_CLK, /* name */
1267 P4_PSI5_S_TRIG2_CLK, /* name */
1277 P4_PSI5_S_TRIG3_CLK, /* name */
1287 P4_PSI5_S_UART_CLK, /* name */
1297 P4_PSI5_S_UTIL_CLK, /* name */
1307 P4_PSI5_S_WDOG0_CLK, /* name */
1317 P4_PSI5_S_WDOG1_CLK, /* name */
1327 P4_PSI5_S_WDOG2_CLK, /* name */
1337 P4_PSI5_S_WDOG3_CLK, /* name */
1347 P4_QSPI0_2X_CLK, /* name */
1357 P4_QSPI1_2X_CLK, /* name */
1367 P5_AE_CLK, /* name */
1377 P5_CANXL_PE_CLK, /* name */
1387 P5_CANXL_CHI_CLK, /* name */
1397 CLKOUT3_CLK, /* name */
1407 P5_LIN_BAUD_CLK, /* name */
1417 P5_REG_INTF_CLK, /* name */
1427 P5_SYS_CLK, /* name */
1437 P6_REG_INTF_CLK, /* name */
1447 PERIPHPLL_PHI0_CLK, /* name */
1457 PERIPHPLL_PHI1_CLK, /* name */
1467 PERIPHPLL_PHI2_CLK, /* name */
1477 PERIPHPLL_PHI3_CLK, /* name */
1487 PERIPHPLL_PHI4_CLK, /* name */
1497 PERIPHPLL_PHI5_CLK, /* name */
1507 PERIPHPLL_PHI6_CLK, /* name */
1517 RTU0_CORE_CLK, /* name */
1527 RTU0_REG_INTF_CLK, /* name */
1537 RTU1_CORE_CLK, /* name */
1547 RTU1_REG_INTF_CLK, /* name */
1557 P4_SDHC_CLK, /* name */
1571 P0_GTM_CLK, /* divider name */
1573 P0_GTM_CLK, /* input source name */
1583 COREPLL_DFS0_CLK, /* name */
1594 COREPLL_DFS1_CLK, /* name */
1605 COREPLL_DFS2_CLK, /* name */
1616 COREPLL_DFS3_CLK, /* name */
1627 COREPLL_DFS4_CLK, /* name */
1638 COREPLL_DFS5_CLK, /* name */
1649 PERIPHPLL_DFS0_CLK, /* name */
1660 PERIPHPLL_DFS1_CLK, /* name */
1671 PERIPHPLL_DFS2_CLK, /* name */
1682 PERIPHPLL_DFS3_CLK, /* name */
1693 PERIPHPLL_DFS4_CLK, /* name */
1704 PERIPHPLL_DFS5_CLK, /* name */
1719 ETH_RGMII_REF_CLK, /* name */
1726 TMR_1588_CLK, /* name */
1733 ETH0_EXT_RX_CLK, /* name */
1740 ETH0_EXT_TX_CLK, /* name */
1747 ETH1_EXT_RX_CLK, /* name */
1754 ETH1_EXT_TX_CLK, /* name */
1761 LFAST0_EXT_REF_CLK, /* name */
1768 LFAST1_EXT_REF_CLK, /* name */
1779 DDR_CLK, /* name */
1786 ADC0_CLK, /* name */
1793 ADC1_CLK, /* name */
1800 CE_EDMA_CLK, /* name */
1807 CE_PIT0_CLK, /* name */
1814 CE_PIT1_CLK, /* name */
1821 CE_PIT2_CLK, /* name */
1828 CE_PIT3_CLK, /* name */
1835 CE_PIT4_CLK, /* name */
1842 CE_PIT5_CLK, /* name */
1849 CTU_CLK, /* name */
1856 DMACRC0_CLK, /* name */
1863 DMACRC1_CLK, /* name */
1870 DMACRC4_CLK, /* name */
1877 DMACRC5_CLK, /* name */
1884 DMAMUX0_CLK, /* name */
1891 DMAMUX1_CLK, /* name */
1898 DMAMUX4_CLK, /* name */
1905 DMAMUX5_CLK, /* name */
1912 EDMA0_CLK, /* name */
1919 EDMA1_CLK, /* name */
1926 EDMA3_CLK, /* name */
1933 EDMA4_CLK, /* name */
1940 EDMA5_CLK, /* name */
1947 ENET0_CLK, /* name */
1954 FLEXCAN0_CLK, /* name */
1961 FLEXCAN1_CLK, /* name */
1968 FLEXCAN2_CLK, /* name */
1975 FLEXCAN3_CLK, /* name */
1982 FLEXCAN4_CLK, /* name */
1989 FLEXCAN5_CLK, /* name */
1996 FLEXCAN6_CLK, /* name */
2003 FLEXCAN7_CLK, /* name */
2010 FLEXCAN8_CLK, /* name */
2017 FLEXCAN9_CLK, /* name */
2024 FLEXCAN10_CLK, /* name */
2031 FLEXCAN11_CLK, /* name */
2038 FLEXCAN12_CLK, /* name */
2045 FLEXCAN13_CLK, /* name */
2052 FLEXCAN14_CLK, /* name */
2059 FLEXCAN15_CLK, /* name */
2066 FLEXCAN16_CLK, /* name */
2073 FLEXCAN17_CLK, /* name */
2080 FLEXCAN18_CLK, /* name */
2087 FLEXCAN19_CLK, /* name */
2094 FLEXCAN20_CLK, /* name */
2101 FLEXCAN21_CLK, /* name */
2108 FLEXCAN22_CLK, /* name */
2115 FLEXCAN23_CLK, /* name */
2122 FRAY0_CLK, /* name */
2129 FRAY1_CLK, /* name */
2136 GTM_CLK, /* name */
2143 IIIC0_CLK, /* name */
2150 IIIC1_CLK, /* name */
2157 IIIC2_CLK, /* name */
2164 LIN0_CLK, /* name */
2171 LIN1_CLK, /* name */
2178 LIN2_CLK, /* name */
2185 LIN3_CLK, /* name */
2192 LIN4_CLK, /* name */
2199 LIN5_CLK, /* name */
2206 LIN6_CLK, /* name */
2213 LIN7_CLK, /* name */
2220 LIN8_CLK, /* name */
2227 LIN9_CLK, /* name */
2234 LIN10_CLK, /* name */
2241 LIN11_CLK, /* name */
2248 MSCDSPI_CLK, /* name */
2255 MSCLIN_CLK, /* name */
2262 NANO_CLK, /* name */
2269 PIT0_CLK, /* name */
2276 PIT1_CLK, /* name */
2283 PIT4_CLK, /* name */
2290 PIT5_CLK, /* name */
2297 PSI5_0_CLK, /* name */
2304 PSI5_1_CLK, /* name */
2311 PSI5S_0_CLK, /* name */
2318 PSI5S_1_CLK, /* name */
2325 QSPI0_CLK, /* name */
2332 QSPI1_CLK, /* name */
2339 RXLUT_CLK, /* name */
2346 SDHC0_CLK, /* name */
2353 SINC_CLK, /* name */
2360 SIPI0_CLK, /* name */
2367 SIPI1_CLK, /* name */
2374 SIUL2_0_CLK, /* name */
2381 SIUL2_1_CLK, /* name */
2388 SIUL2_4_CLK, /* name */
2395 SIUL2_5_CLK, /* name */
2402 SPI0_CLK, /* name */
2409 SPI1_CLK, /* name */
2416 SPI2_CLK, /* name */
2423 SPI3_CLK, /* name */
2430 SPI4_CLK, /* name */
2437 SPI5_CLK, /* name */
2444 SPI6_CLK, /* name */
2451 SPI7_CLK, /* name */
2458 SPI8_CLK, /* name */
2465 SPI9_CLK, /* name */
2472 SRX0_CLK, /* name */
2479 SRX1_CLK, /* name */
2491 P2_SYS_CLK, /* Clock name associated to clock monitor. */
2509 P0_REG_INTF_CLK, /* Clock name associated to clock monitor. */
2527 P1_REG_INTF_CLK, /* Clock name associated to clock monitor. */
2545 FIRC_CLK, /* Clock name associated to clock monitor. */
2563 FXOSC_CLK, /* Clock name associated to clock monitor. */
2581 P2_MATH_CLK, /* Clock name associated to clock monitor. */
2599 P3_SYS_MON1_CLK, /* Clock name associated to clock monitor. */
2617 P4_REG_INTF_CLK, /* Clock name associated to clock monitor. */
2635 P5_REG_INTF_CLK, /* Clock name associated to clock monitor. */
2653 DDR_CLK, /* Clock name associated to clock monitor. */
2671 P3_SYS_MON2_CLK, /* Clock name associated to clock monitor. */
2689 P3_SYS_MON3_CLK, /* Clock name associated to clock monitor. */
2707 CE_SYS_DIV2_CLK, /* Clock name associated to clock monitor. */
2725 P0_CLKOUT_SRC_CLK, /* Clock name associated to clock monitor. */
2743 P1_CLKOUT_SRC_CLK, /* Clock name associated to clock monitor. */