Lines Matching refs:U
153 #if CLOCK_IP_CONFIGURED_IRCOSCS_0_NO > 0U
157 0U, /* Enable regulator */
159 0U, /* Ircosc enable in VLP mode */
160 0U, /* Ircosc enable in STOP mode */
167 0U, /* Disabled in standby mode. */
168 0U, /* Enable regulator */
169 0U, /* Ircosc range */
170 0U, /* Ircosc enable in VLP mode */
171 0U, /* Ircosc enable in STOP mode */
178 0U, /* Disabled in standby mode. */
179 0U, /* Enable regulator */
180 0U, /* Ircosc range */
181 0U, /* Ircosc enable in VLP mode */
182 0U, /* Ircosc enable in STOP mode */
190 #if CLOCK_IP_CONFIGURED_XOSCS_0_NO > 0U
196 0U, /* bypassOption: Xosc use crystal */
199 0U, /* Gain value */
200 0U, /* Monitor type */
201 0U, /* Automatic level controller */
211 0U, /* bypassOption */
212 0U, /* Comparator is not enabled */
213 0U, /* Crystal overdrive protection */
214 0U, /* Gain value */
215 0U, /* Monitor type */
216 0U, /* Automatic level controller */
224 #if CLOCK_IP_CONFIGURED_PLLS_0_NO > 0U
229 0U, /* Bypass */
231 0U, /* multiplier */
232 0U, /* postdivider */
233 0U, /* numeratorFracLoopDiv */
236 0U, /* Modulation type: Spread spectrum modulation bypassed */
237 0U, /* modulationPeriod */
238 0U, /* incrementStep */
239 0U, /* sigmaDelta */
240 0U, /* ditherControl */
241 0U, /* ditherControlValue */
242 0U, /* Monitor type */
244 0U,
245 0U,
246 0U,
255 #if CLOCK_IP_CONFIGURED_SELECTORS_0_NO > 0U
350 #if CLOCK_IP_CONFIGURED_DIVIDERS_0_NO > 0U
355 0U,
366 0U,
376 0U,
386 0U,
396 0U,
406 0U,
416 0U,
426 0U,
436 0U,
446 0U,
456 0U,
466 0U,
476 0U,
486 0U,
496 0U,
506 0U,
516 0U,
526 0U,
536 0U,
546 0U,
556 0U,
565 #if CLOCK_IP_CONFIGURED_DIVIDER_TRIGGERS_0_NO > 0U
577 #if CLOCK_IP_CONFIGURED_EXT_CLKS_0_NO > 0U
580 0U, /* value */
587 0U, /* value */
595 #if CLOCK_IP_CONFIGURED_GATES_0_NO > 0U
1299 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U
1302 0U, /*Enable/disable clock monitor CMU_FC_0 */
1304 CMU_FC_IER_FLLIE(0U) |
1305 CMU_FC_IER_FHHIE(0U) |
1306 CMU_FC_IER_FLLAIE(0U) |
1307 CMU_FC_IER_FHHAIE(0U)
1311 0U, /* Start index in register values array */
1312 0U, /* End index in register values array */
1316 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U
1319 0U, /*Enable/disable clock monitor CMU_FC_3 */
1321 CMU_FC_IER_FLLIE(0U) |
1322 CMU_FC_IER_FHHIE(0U) |
1323 CMU_FC_IER_FLLAIE(0U) |
1324 CMU_FC_IER_FHHAIE(0U)
1328 0U, /* Start index in register values array */
1329 0U, /* End index in register values array */
1333 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U
1336 0U, /*Enable/disable clock monitor CMU_FC_4 */
1338 CMU_FC_IER_FLLIE(0U) |
1339 CMU_FC_IER_FHHIE(0U) |
1340 CMU_FC_IER_FLLAIE(0U) |
1341 CMU_FC_IER_FHHAIE(0U)
1345 0U, /* Start index in register values array */
1346 0U, /* End index in register values array */
1350 #if CLOCK_IP_CONFIGURED_CMUS_0_NO > 0U
1353 0U, /*Enable/disable clock monitor CMU_FC_5 */
1355 CMU_FC_IER_FLLIE(0U) |
1356 CMU_FC_IER_FHHIE(0U) |
1357 CMU_FC_IER_FLLAIE(0U) |
1358 CMU_FC_IER_FHHAIE(0U)
1362 0U, /* Start index in register values array */
1363 0U, /* End index in register values array */
1374 0U,
1410 #if CLOCK_IP_CONFIGURED_SELECTORS_1_NO > 0U
1435 #if CLOCK_IP_CONFIGURED_DIVIDERS_1_NO > 0U
1440 0U,
1450 0U,
1460 0U,
1469 #if CLOCK_IP_CONFIGURED_EXT_CLKS_1_NO > 0U
1472 0U, /* value */
1487 #if CLOCK_IP_CONFIGURED_GATES_1_NO > 0U
2191 #if CLOCK_IP_CONFIGURED_CMUS_1_NO > 0U
2194 0U, /*Enable/disable clock monitor CMU_FC_0 */
2196 CMU_FC_IER_FLLIE(0U) |
2197 CMU_FC_IER_FHHIE(0U) |
2198 CMU_FC_IER_FLLAIE(0U) |
2199 CMU_FC_IER_FHHAIE(0U)
2203 0U, /* Start index in register values array */
2204 0U, /* End index in register values array */
2208 #if CLOCK_IP_CONFIGURED_CMUS_1_NO > 0U
2211 0U, /*Enable/disable clock monitor CMU_FC_3 */
2213 CMU_FC_IER_FLLIE(0U) |
2214 CMU_FC_IER_FHHIE(0U) |
2215 CMU_FC_IER_FLLAIE(0U) |
2216 CMU_FC_IER_FHHAIE(0U)
2220 0U, /* Start index in register values array */
2221 0U, /* End index in register values array */
2225 #if CLOCK_IP_CONFIGURED_CMUS_1_NO > 0U
2228 0U, /*Enable/disable clock monitor CMU_FC_4 */
2230 CMU_FC_IER_FLLIE(0U) |
2231 CMU_FC_IER_FHHIE(0U) |
2232 CMU_FC_IER_FLLAIE(0U) |
2233 CMU_FC_IER_FHHAIE(0U)
2237 0U, /* Start index in register values array */
2238 0U, /* End index in register values array */
2242 #if CLOCK_IP_CONFIGURED_CMUS_1_NO > 0U
2245 0U, /*Enable/disable clock monitor CMU_FC_5 */
2247 CMU_FC_IER_FLLIE(0U) |
2248 CMU_FC_IER_FHHIE(0U) |
2249 CMU_FC_IER_FLLAIE(0U) |
2250 CMU_FC_IER_FHHAIE(0U)
2254 0U, /* Start index in register values array */
2255 0U, /* End index in register values array */
2266 0U,
2309 0U, /* clkConfigId */
2318 0U, /* fracDivsCount */
2321 0U, /* pcfsCount */
2345 0U, /* ircoscsCount */
2346 0U, /* xoscsCount */
2347 0U, /* pllsCount */
2350 0U, /* dividerTriggersCount */
2351 0U, /* fracDivsCount */
2354 0U, /* pcfsCount */