Lines Matching full:name
155 FIRC_CLK, /* name */
166 FIRC_STANDBY_CLK, /* name */
177 SIRC_STANDBY_CLK, /* name */
192 FXOSC_CLK, /* name */
207 SXOSC_CLK, /* name */
226 PLL_CLK, /* name */
257 SCS_CLK, /* Clock name associated to selector */
258 PLL_PHI0_CLK, /* Name of the selected input source */
264 CLKOUT_RUN_CLK, /* Clock name associated to selector */
265 FXOSC_CLK, /* Name of the selected input source */
271 CLKOUT_STANDBY_CLK, /* Clock name associated to selector */
272 FIRC_CLK, /* Name of the selected input source */
278 EMAC_RX_CLK, /* Clock name associated to selector */
279 FIRC_CLK, /* Name of the selected input source */
285 EMAC_TS_CLK, /* Clock name associated to selector */
286 FIRC_CLK, /* Name of the selected input source */
292 EMAC_TX_CLK, /* Clock name associated to selector */
293 FIRC_CLK, /* Name of the selected input source */
299 FLEXCANA_CLK, /* Clock name associated to selector */
300 AIPS_PLAT_CLK, /* Name of the selected input source */
306 FLEXCANB_CLK, /* Clock name associated to selector */
307 AIPS_PLAT_CLK, /* Name of the selected input source */
313 QSPI_SFCK_CLK, /* Clock name associated to selector */
314 FIRC_CLK, /* Name of the selected input source */
320 RTC_CLK, /* Clock name associated to selector */
321 SXOSC_CLK, /* Name of the selected input source */
327 STMA_CLK, /* Clock name associated to selector */
328 FIRC_CLK, /* Name of the selected input source */
334 STMB_CLK, /* Clock name associated to selector */
335 FIRC_CLK, /* Name of the selected input source */
341 TRACE_CLK, /* Clock name associated to selector */
342 FIRC_CLK, /* Name of the selected input source */
352 PLL_POSTDIV_CLK, /* name */
363 PLL_PHI0_CLK, /* name */
373 PLL_PHI1_CLK, /* name */
383 CORE_CLK, /* name */
393 AIPS_PLAT_CLK, /* name */
403 AIPS_SLOW_CLK, /* name */
413 HSE_CLK, /* name */
423 DCM_CLK, /* name */
433 LBIST_CLK, /* name */
443 QSPI_MEM_CLK, /* name */
453 CLKOUT_RUN_CLK, /* name */
463 CLKOUT_STANDBY_CLK, /* name */
473 EMAC_RX_CLK, /* name */
483 EMAC_TS_CLK, /* name */
493 EMAC_TX_CLK, /* name */
503 FLEXCANA_CLK, /* name */
513 FLEXCANB_CLK, /* name */
523 QSPI_SFCK_CLK, /* name */
533 STMA_CLK, /* name */
543 STMB_CLK, /* name */
553 TRACE_CLK, /* name */
567 CORE_CLK, /* divider name */
569 CORE_CLK, /* input source name */
579 EMAC_MII_RX_CLK, /* name */
586 EMAC_MII_RMII_TX_CLK, /* name */
597 ADC0_CLK, /* name */
604 ADC1_CLK, /* name */
611 ADC2_CLK, /* name */
618 BCTU0_CLK, /* name */
625 CMP0_CLK, /* name */
632 CMP1_CLK, /* name */
639 CMP2_CLK, /* name */
646 CRC0_CLK, /* name */
653 DMAMUX0_CLK, /* name */
660 DMAMUX1_CLK, /* name */
667 EDMA0_CLK, /* name */
674 EDMA0_TCD0_CLK, /* name */
681 EDMA0_TCD1_CLK, /* name */
688 EDMA0_TCD2_CLK, /* name */
695 EDMA0_TCD3_CLK, /* name */
702 EDMA0_TCD4_CLK, /* name */
709 EDMA0_TCD5_CLK, /* name */
716 EDMA0_TCD6_CLK, /* name */
723 EDMA0_TCD7_CLK, /* name */
730 EDMA0_TCD8_CLK, /* name */
737 EDMA0_TCD9_CLK, /* name */
744 EDMA0_TCD10_CLK, /* name */
751 EDMA0_TCD11_CLK, /* name */
758 EDMA0_TCD12_CLK, /* name */
765 EDMA0_TCD13_CLK, /* name */
772 EDMA0_TCD14_CLK, /* name */
779 EDMA0_TCD15_CLK, /* name */
786 EDMA0_TCD16_CLK, /* name */
793 EDMA0_TCD17_CLK, /* name */
800 EDMA0_TCD18_CLK, /* name */
807 EDMA0_TCD19_CLK, /* name */
814 EDMA0_TCD20_CLK, /* name */
821 EDMA0_TCD21_CLK, /* name */
828 EDMA0_TCD22_CLK, /* name */
835 EDMA0_TCD23_CLK, /* name */
842 EDMA0_TCD24_CLK, /* name */
849 EDMA0_TCD25_CLK, /* name */
856 EDMA0_TCD26_CLK, /* name */
863 EDMA0_TCD27_CLK, /* name */
870 EDMA0_TCD28_CLK, /* name */
877 EDMA0_TCD29_CLK, /* name */
884 EDMA0_TCD30_CLK, /* name */
891 EDMA0_TCD31_CLK, /* name */
898 EIM_CLK, /* name */
905 EMAC0_RX_CLK, /* name */
912 EMIOS0_CLK, /* name */
919 EMIOS1_CLK, /* name */
926 EMIOS2_CLK, /* name */
933 ERM0_CLK, /* name */
940 FLEXCAN0_CLK, /* name */
947 FLEXCAN1_CLK, /* name */
954 FLEXCAN2_CLK, /* name */
961 FLEXCAN3_CLK, /* name */
968 FLEXCAN4_CLK, /* name */
975 FLEXCAN5_CLK, /* name */
982 FLEXIO0_CLK, /* name */
989 INTM_CLK, /* name */
996 LCU0_CLK, /* name */
1003 LCU1_CLK, /* name */
1010 LPI2C0_CLK, /* name */
1017 LPI2C1_CLK, /* name */
1024 LPSPI0_CLK, /* name */
1031 LPSPI1_CLK, /* name */
1038 LPSPI2_CLK, /* name */
1045 LPSPI3_CLK, /* name */
1052 LPSPI4_CLK, /* name */
1059 LPSPI5_CLK, /* name */
1066 LPUART0_CLK, /* name */
1073 LPUART1_CLK, /* name */
1080 LPUART2_CLK, /* name */
1087 LPUART3_CLK, /* name */
1094 LPUART4_CLK, /* name */
1101 LPUART5_CLK, /* name */
1108 LPUART6_CLK, /* name */
1115 LPUART7_CLK, /* name */
1122 LPUART8_CLK, /* name */
1129 LPUART9_CLK, /* name */
1136 LPUART10_CLK, /* name */
1143 LPUART11_CLK, /* name */
1150 LPUART12_CLK, /* name */
1157 LPUART13_CLK, /* name */
1164 LPUART14_CLK, /* name */
1171 LPUART15_CLK, /* name */
1178 MSCM_CLK, /* name */
1185 PIT0_CLK, /* name */
1192 PIT1_CLK, /* name */
1199 PIT2_CLK, /* name */
1206 QSPI0_RAM_CLK, /* name */
1213 RTC0_CLK, /* name */
1220 SAI0_CLK, /* name */
1227 SAI1_CLK, /* name */
1234 SEMA42_CLK, /* name */
1241 SIUL2_CLK, /* name */
1248 STM0_CLK, /* name */
1255 STM1_CLK, /* name */
1262 SWT0_CLK, /* name */
1269 TEMPSENSE_CLK, /* name */
1276 TRGMUX0_CLK, /* name */
1283 TSENSE0_CLK, /* name */
1290 WKPU0_CLK, /* name */
1301 FXOSC_CLK, /* Clock name associated to clock monitor. */
1318 CORE_CLK, /* Clock name associated to clock monitor. */
1335 AIPS_PLAT_CLK, /* Clock name associated to clock monitor. */
1352 HSE_CLK, /* Clock name associated to clock monitor. */
1412 EMAC_RX_CLK, /* Clock name associated to selector */
1413 EMAC_MII_RMII_TX_CLK, /* Name of the selected input source */
1419 EMAC_TS_CLK, /* Clock name associated to selector */
1420 FIRC_CLK, /* Name of the selected input source */
1426 EMAC_TX_CLK, /* Clock name associated to selector */
1427 EMAC_MII_RMII_TX_CLK, /* Name of the selected input source */
1437 EMAC_RX_CLK, /* name */
1447 EMAC_TS_CLK, /* name */
1457 EMAC_TX_CLK, /* name */
1471 EMAC_MII_RX_CLK, /* name */
1478 EMAC_MII_RMII_TX_CLK, /* name */
1489 ADC0_CLK, /* name */
1496 ADC1_CLK, /* name */
1503 ADC2_CLK, /* name */
1510 BCTU0_CLK, /* name */
1517 CMP0_CLK, /* name */
1524 CMP1_CLK, /* name */
1531 CMP2_CLK, /* name */
1538 CRC0_CLK, /* name */
1545 DMAMUX0_CLK, /* name */
1552 DMAMUX1_CLK, /* name */
1559 EDMA0_CLK, /* name */
1566 EDMA0_TCD0_CLK, /* name */
1573 EDMA0_TCD1_CLK, /* name */
1580 EDMA0_TCD2_CLK, /* name */
1587 EDMA0_TCD3_CLK, /* name */
1594 EDMA0_TCD4_CLK, /* name */
1601 EDMA0_TCD5_CLK, /* name */
1608 EDMA0_TCD6_CLK, /* name */
1615 EDMA0_TCD7_CLK, /* name */
1622 EDMA0_TCD8_CLK, /* name */
1629 EDMA0_TCD9_CLK, /* name */
1636 EDMA0_TCD10_CLK, /* name */
1643 EDMA0_TCD11_CLK, /* name */
1650 EDMA0_TCD12_CLK, /* name */
1657 EDMA0_TCD13_CLK, /* name */
1664 EDMA0_TCD14_CLK, /* name */
1671 EDMA0_TCD15_CLK, /* name */
1678 EDMA0_TCD16_CLK, /* name */
1685 EDMA0_TCD17_CLK, /* name */
1692 EDMA0_TCD18_CLK, /* name */
1699 EDMA0_TCD19_CLK, /* name */
1706 EDMA0_TCD20_CLK, /* name */
1713 EDMA0_TCD21_CLK, /* name */
1720 EDMA0_TCD22_CLK, /* name */
1727 EDMA0_TCD23_CLK, /* name */
1734 EDMA0_TCD24_CLK, /* name */
1741 EDMA0_TCD25_CLK, /* name */
1748 EDMA0_TCD26_CLK, /* name */
1755 EDMA0_TCD27_CLK, /* name */
1762 EDMA0_TCD28_CLK, /* name */
1769 EDMA0_TCD29_CLK, /* name */
1776 EDMA0_TCD30_CLK, /* name */
1783 EDMA0_TCD31_CLK, /* name */
1790 EIM_CLK, /* name */
1797 EMAC0_RX_CLK, /* name */
1804 EMIOS0_CLK, /* name */
1811 EMIOS1_CLK, /* name */
1818 EMIOS2_CLK, /* name */
1825 ERM0_CLK, /* name */
1832 FLEXCAN0_CLK, /* name */
1839 FLEXCAN1_CLK, /* name */
1846 FLEXCAN2_CLK, /* name */
1853 FLEXCAN3_CLK, /* name */
1860 FLEXCAN4_CLK, /* name */
1867 FLEXCAN5_CLK, /* name */
1874 FLEXIO0_CLK, /* name */
1881 INTM_CLK, /* name */
1888 LCU0_CLK, /* name */
1895 LCU1_CLK, /* name */
1902 LPI2C0_CLK, /* name */
1909 LPI2C1_CLK, /* name */
1916 LPSPI0_CLK, /* name */
1923 LPSPI1_CLK, /* name */
1930 LPSPI2_CLK, /* name */
1937 LPSPI3_CLK, /* name */
1944 LPSPI4_CLK, /* name */
1951 LPSPI5_CLK, /* name */
1958 LPUART0_CLK, /* name */
1965 LPUART1_CLK, /* name */
1972 LPUART2_CLK, /* name */
1979 LPUART3_CLK, /* name */
1986 LPUART4_CLK, /* name */
1993 LPUART5_CLK, /* name */
2000 LPUART6_CLK, /* name */
2007 LPUART7_CLK, /* name */
2014 LPUART8_CLK, /* name */
2021 LPUART9_CLK, /* name */
2028 LPUART10_CLK, /* name */
2035 LPUART11_CLK, /* name */
2042 LPUART12_CLK, /* name */
2049 LPUART13_CLK, /* name */
2056 LPUART14_CLK, /* name */
2063 LPUART15_CLK, /* name */
2070 MSCM_CLK, /* name */
2077 PIT0_CLK, /* name */
2084 PIT1_CLK, /* name */
2091 PIT2_CLK, /* name */
2098 QSPI0_RAM_CLK, /* name */
2105 RTC0_CLK, /* name */
2112 SAI0_CLK, /* name */
2119 SAI1_CLK, /* name */
2126 SEMA42_CLK, /* name */
2133 SIUL2_CLK, /* name */
2140 STM0_CLK, /* name */
2147 STM1_CLK, /* name */
2154 SWT0_CLK, /* name */
2161 TEMPSENSE_CLK, /* name */
2168 TRGMUX0_CLK, /* name */
2175 TSENSE0_CLK, /* name */
2182 WKPU0_CLK, /* name */
2193 FXOSC_CLK, /* Clock name associated to clock monitor. */
2210 CORE_CLK, /* Clock name associated to clock monitor. */
2227 AIPS_PLAT_CLK, /* Clock name associated to clock monitor. */
2244 HSE_CLK, /* Clock name associated to clock monitor. */