Lines Matching full:name
133 SIRC_CLK, /* name */
144 FIRC_CLK, /* name */
160 SOSC_CLK, /* Clock name associated to xosc */
180 SPLL_CLK, /* name */
213 SCS_RUN_CLK, /* Clock name associated to selector */
214 SPLL_CLK, /* Name of the selected input source */
220 SCS_VLPR_CLK, /* Clock name associated to selector */
221 SIRC_CLK, /* Name of the selected input source */
227 SCS_HSRUN_CLK, /* Clock name associated to selector */
228 FIRC_CLK, /* Name of the selected input source */
234 SCG_CLKOUT_CLK, /* Clock name associated to selector */
235 SPLL_CLK, /* Name of the selected input source */
241 RTC_CLK, /* Clock name associated to selector */
242 LPO_32K_CLK, /* Name of the selected input source */
248 LPO_CLK, /* Clock name associated to selector */
249 LPO_128K_CLK, /* Name of the selected input source */
255 TRACE_CLK, /* Clock name associated to selector */
256 CORE_CLK, /* Name of the selected input source */
262 CLKOUT0_CLK, /* Clock name associated to selector */
263 HCLK, /* Name of the selected input source */
269 FTM0_EXT_CLK, /* Clock name associated to selector */
270 TCLK0_REF_CLK, /* Name of the selected input source */
276 FTM1_EXT_CLK, /* Clock name associated to selector */
277 TCLK0_REF_CLK, /* Name of the selected input source */
283 FTM2_EXT_CLK, /* Clock name associated to selector */
284 TCLK0_REF_CLK, /* Name of the selected input source */
290 FTM3_EXT_CLK, /* Clock name associated to selector */
291 TCLK0_REF_CLK, /* Name of the selected input source */
297 FTM4_EXT_CLK, /* Clock name associated to selector */
298 TCLK0_REF_CLK, /* Name of the selected input source */
304 FTM5_EXT_CLK, /* Clock name associated to selector */
305 TCLK0_REF_CLK, /* Name of the selected input source */
311 FTM0_CLK, /* Clock name associated to selector */
312 SPLLDIV1_CLK, /* Name of the selected input source */
318 FTM1_CLK, /* Clock name associated to selector */
319 SPLLDIV1_CLK, /* Name of the selected input source */
325 FTM2_CLK, /* Clock name associated to selector */
326 SPLLDIV1_CLK, /* Name of the selected input source */
332 FTM3_CLK, /* Clock name associated to selector */
333 SPLLDIV1_CLK, /* Name of the selected input source */
339 FTM4_CLK, /* Clock name associated to selector */
340 SPLLDIV1_CLK, /* Name of the selected input source */
346 FTM5_CLK, /* Clock name associated to selector */
347 SPLLDIV1_CLK, /* Name of the selected input source */
353 ADC1_CLK, /* Clock name associated to selector */
354 SPLLDIV2_CLK, /* Name of the selected input source */
360 LPSPI0_CLK, /* Clock name associated to selector */
361 SPLLDIV2_CLK, /* Name of the selected input source */
367 LPSPI1_CLK, /* Clock name associated to selector */
368 SPLLDIV2_CLK, /* Name of the selected input source */
374 LPSPI2_CLK, /* Clock name associated to selector */
375 SPLLDIV2_CLK, /* Name of the selected input source */
381 LPIT0_CLK, /* Clock name associated to selector */
382 SPLLDIV2_CLK, /* Name of the selected input source */
388 ADC0_CLK, /* Clock name associated to selector */
389 SPLLDIV2_CLK, /* Name of the selected input source */
395 FlexIO_CLK, /* Clock name associated to selector */
396 SPLLDIV2_CLK, /* Name of the selected input source */
402 LPI2C0_CLK, /* Clock name associated to selector */
403 SPLLDIV2_CLK, /* Name of the selected input source */
409 LPUART0_CLK, /* Clock name associated to selector */
410 SPLLDIV2_CLK, /* Name of the selected input source */
416 LPUART1_CLK, /* Clock name associated to selector */
417 SPLLDIV2_CLK, /* Name of the selected input source */
423 LPUART2_CLK, /* Clock name associated to selector */
424 SPLLDIV2_CLK, /* Name of the selected input source */
430 LPTMR0_CLK, /* Clock name associated to selector */
431 SPLLDIV2_CLK, /* Name of the selected input source */
443 SIRCDIV1_CLK, /* name */
453 SIRCDIV2_CLK, /* name */
463 FIRCDIV1_CLK, /* name */
473 FIRCDIV2_CLK, /* name */
483 SOSCDIV1_CLK, /* name */
493 SOSCDIV2_CLK, /* name */
503 SPLLDIV1_CLK, /* name */
513 SPLLDIV2_CLK, /* name */
523 CORE_RUN_CLK, /* name */
533 CORE_VLPR_CLK, /* name */
543 CORE_HSRUN_CLK, /* name */
553 BUS_RUN_CLK, /* name */
563 BUS_VLPR_CLK, /* name */
573 BUS_HSRUN_CLK, /* name */
583 SLOW_RUN_CLK, /* name */
593 SLOW_VLPR_CLK, /* name */
603 SLOW_HSRUN_CLK, /* name */
613 CLKOUT0_CLK, /* name */
623 LPTMR0_CLK, /* name */
633 TRACE_CLK, /* name */
645 RESERVED_CLK, /* divider name */
647 RESERVED_CLK, /* input source name */
672 TCLK0_REF_CLK, /* name */
679 TCLK1_REF_CLK, /* name */
686 TCLK2_REF_CLK, /* name */
693 RTC_CLKIN, /* name */
706 LPO_32K_CLK, /* name */
713 LPO_1K_CLK, /* name */
720 ADC0_CLK, /* name */
727 ADC1_CLK, /* name */
734 CLKOUT0_CLK, /* name */
741 CMP0_CLK, /* name */
748 CRC0_CLK, /* name */
755 DMA0_CLK, /* name */
762 DMAMUX0_CLK, /* name */
769 EIM0_CLK, /* name */
776 ERM0_CLK, /* name */
783 EWM0_CLK, /* name */
790 FLEXCAN0_CLK, /* name */
797 FLEXCAN1_CLK, /* name */
804 FLEXCAN2_CLK, /* name */
811 FlexIO_CLK, /* name */
818 FTFC_CLK, /* name */
825 FTM0_CLK, /* name */
832 FTM1_CLK, /* name */
839 FTM2_CLK, /* name */
846 FTM3_CLK, /* name */
853 FTM4_CLK, /* name */
860 FTM5_CLK, /* name */
867 LPI2C0_CLK, /* name */
874 LPIT0_CLK, /* name */
881 LPSPI0_CLK, /* name */
888 LPSPI1_CLK, /* name */
895 LPSPI2_CLK, /* name */
902 LPTMR0_CLK, /* name */
909 LPUART0_CLK, /* name */
916 LPUART1_CLK, /* name */
923 LPUART2_CLK, /* name */
930 MPU0_CLK, /* name */
937 MSCM0_CLK, /* name */
944 PDB0_CLK, /* name */
951 PDB1_CLK, /* name */
958 PORTA_CLK, /* name */
965 PORTB_CLK, /* name */
972 PORTC_CLK, /* name */
979 PORTD_CLK, /* name */
986 PORTE_CLK, /* name */
993 RTC0_CLK, /* name */
1000 TRACE_CLK, /* name */