387     uint32_t timing;  in SEMC_ConfigureSDRAM()  local
448     timing = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz));  in SEMC_ConfigureSDRAM()
449     timing |= SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz));  in SEMC_ConfigureSDRAM()
450     timing |= SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz));  in SEMC_ConfigureSDRAM()
451     timing |= SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz));  in SEMC_ConfigureSDRAM()
452     timing |= SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz));  in SEMC_ConfigureSDRAM()
453     timing |= SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz));  in SEMC_ConfigureSDRAM()
455     base->SDRAMCR1 = timing;  in SEMC_ConfigureSDRAM()
457     timing = SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz));  in SEMC_ConfigureSDRAM()
458     timing |= SEMC_SDRAMCR2_REF2REF(SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz));  in SEMC_ConfigureSDRAM()
459 …timing |= SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | SEMC_SDRAMCR…  in SEMC_ConfigureSDRAM()
461     base->SDRAMCR2 = timing;  in SEMC_ConfigureSDRAM()
517     uint32_t timing;  in SEMC_ConfigureNAND()  local
571     timing = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
572     timing |= SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
573     timing |= SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
574     timing |= SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
575     timing |= SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
576     timing |= SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
577     timing |= SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
578 … timing |= SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
580     base->NANDCR1 = timing;  in SEMC_ConfigureNAND()
582 … timing = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
583 …timing |= SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
584 …timing |= SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz…  in SEMC_ConfigureNAND()
585 …  timing |= SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
586 …  timing |= SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz));  in SEMC_ConfigureNAND()
589     base->NANDCR2 = timing;  in SEMC_ConfigureNAND()
613     uint32_t timing;  in SEMC_ConfigureNOR()  local
710     timing = SEMC_NORCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
711     timing |= SEMC_NORCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
712     timing |= SEMC_NORCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
713     timing |= SEMC_NORCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
714     timing |= SEMC_NORCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
715     timing |= SEMC_NORCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
716     timing |= SEMC_NORCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
717     timing |= SEMC_NORCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
720     base->NORCR1 = timing;  in SEMC_ConfigureNOR()
722     timing = SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
724     timing |= SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
727     timing |= SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
729     timing |= SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz));  in SEMC_ConfigureNOR()
730 …timing |= SEMC_NORCR2_AWDH((uint32_t)SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 0…  in SEMC_ConfigureNOR()
731 …timing |= SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD((uint32_t)config->readCycle - 0x01…  in SEMC_ConfigureNOR()
734     base->NORCR2 = timing;  in SEMC_ConfigureNOR()
767     uint32_t timing;  in SEMC_ConfigureSRAMWithChipSelection()  local
968         timing = SEMC_SRAMCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
969         timing |= SEMC_SRAMCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
970         timing |= SEMC_SRAMCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
971         timing |= SEMC_SRAMCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
972         timing |= SEMC_SRAMCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
973         timing |= SEMC_SRAMCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
974         timing |= SEMC_SRAMCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
975         timing |= SEMC_SRAMCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
978         base->SRAMCR1 = timing;  in SEMC_ConfigureSRAMWithChipSelection()
980         timing = SEMC_SRAMCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
981 …  timing |= SEMC_SRAMCR2_WDH((uint32_t)SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz) + 1UL);  in SEMC_ConfigureSRAMWithChipSelection()
982         timing |= SEMC_SRAMCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
983         timing |= SEMC_SRAMCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
984 …timing |= SEMC_SRAMCR2_LC(config->latencyCount) | SEMC_SRAMCR2_RD((uint32_t)config->readCycle - 1U…  in SEMC_ConfigureSRAMWithChipSelection()
985         timing |= SEMC_SRAMCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
987 …timing |= SEMC_SRAMCR2_RDH((uint32_t)SEMC_ConvertTiming(config->readHoldTime_Ns, clkSrc_Hz) + 0x01…  in SEMC_ConfigureSRAMWithChipSelection()
991         base->SRAMCR2 = timing;  in SEMC_ConfigureSRAMWithChipSelection()
996         timing = SEMC_SRAMCR5_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
997         timing |= SEMC_SRAMCR5_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
998         timing |= SEMC_SRAMCR5_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
999         timing |= SEMC_SRAMCR5_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1000         timing |= SEMC_SRAMCR5_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1001         timing |= SEMC_SRAMCR5_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1002         timing |= SEMC_SRAMCR5_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1003         timing |= SEMC_SRAMCR5_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1006         base->SRAMCR5 = timing;  in SEMC_ConfigureSRAMWithChipSelection()
1008         timing = SEMC_SRAMCR6_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1009 …  timing |= SEMC_SRAMCR6_WDH((uint32_t)SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz) + 1UL);  in SEMC_ConfigureSRAMWithChipSelection()
1010         timing |= SEMC_SRAMCR6_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1011         timing |= SEMC_SRAMCR6_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1012 …timing |= SEMC_SRAMCR6_LC(config->latencyCount) | SEMC_SRAMCR2_RD((uint32_t)config->readCycle - 1U…  in SEMC_ConfigureSRAMWithChipSelection()
1013         timing |= SEMC_SRAMCR6_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));  in SEMC_ConfigureSRAMWithChipSelection()
1015 …timing |= SEMC_SRAMCR6_RDH((uint32_t)SEMC_ConvertTiming(config->readHoldTime_Ns, clkSrc_Hz) + 0x01…  in SEMC_ConfigureSRAMWithChipSelection()
1019         base->SRAMCR6 = timing;  in SEMC_ConfigureSRAMWithChipSelection()
1039     uint32_t timing;  in SEMC_ConfigureDBI()  local
1065     timing = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz));  in SEMC_ConfigureDBI()
1066     timing |= SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz));  in SEMC_ConfigureDBI()
1067     timing |= SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz));  in SEMC_ConfigureDBI()
1068     timing |= SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureDBI()
1069     timing |= SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz));  in SEMC_ConfigureDBI()
1070     timing |= SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz));  in SEMC_ConfigureDBI()
1072     timing |= SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz));  in SEMC_ConfigureDBI()
1076     base->DBICR1 = timing;  in SEMC_ConfigureDBI()
1079     timing = SEMC_DBICR2_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz));  in SEMC_ConfigureDBI()
1082     base->DBICR2 = timing;  in SEMC_ConfigureDBI()