Lines Matching refs:SPI_T

327 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
328 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
329 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
340 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)  in SPII2S_ENABLE_TX_ZCD()
361 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)  in SPII2S_DISABLE_TX_ZCD()
491 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)  in SPII2S_SET_MONO_RX_CHANNEL()
559 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, …
560 void SPI_Close(SPI_T *spi);
561 void SPI_ClearRxFIFO(SPI_T *spi);
562 void SPI_ClearTxFIFO(SPI_T *spi);
563 void SPI_DisableAutoSS(SPI_T *spi);
564 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
565 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
566 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
567 uint32_t SPI_GetBusClock(SPI_T *spi);
568 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
569 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
570 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
571 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
572 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
574 uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordW…
575 void SPII2S_Close(SPI_T *i2s);
576 void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
577 void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
578 uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
579 void SPII2S_DisableMCLK(SPI_T *i2s);
580 void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);