352 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
353 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
354 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
365 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)  in SPII2S_ENABLE_TX_ZCD()  argument
369         i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;  in SPII2S_ENABLE_TX_ZCD()
373         i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;  in SPII2S_ENABLE_TX_ZCD()
386 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)  in SPII2S_DISABLE_TX_ZCD()  argument
390         i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;  in SPII2S_DISABLE_TX_ZCD()
394         i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;  in SPII2S_DISABLE_TX_ZCD()
405 #define SPII2S_ENABLE_TXDMA(i2s)  ((i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)  argument
414 #define SPII2S_DISABLE_TXDMA(i2s) ((i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk)  argument
423 #define SPII2S_ENABLE_RXDMA(i2s) ((i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)  argument
432 #define SPII2S_DISABLE_RXDMA(i2s) ((i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk)  argument
441 #define SPII2S_ENABLE_TX(i2s) ((i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk)  argument
450 #define SPII2S_DISABLE_TX(i2s) ((i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk)  argument
459 #define SPII2S_ENABLE_RX(i2s) ((i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk)  argument
468 #define SPII2S_DISABLE_RX(i2s) ((i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk)  argument
477 #define SPII2S_ENABLE_TX_MUTE(i2s)  ((i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk)  argument
486 #define SPII2S_DISABLE_TX_MUTE(i2s) ((i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk)  argument
495 #define SPII2S_CLR_TX_FIFO(i2s) ((i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk)  argument
504 #define SPII2S_CLR_RX_FIFO(i2s) ((i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk)  argument
516 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)  in SPII2S_SET_MONO_RX_CHANNEL()  argument
519     (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :  in SPII2S_SET_MONO_RX_CHANNEL()
520     (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);  in SPII2S_SET_MONO_RX_CHANNEL()
531 #define SPII2S_WRITE_TX_FIFO(i2s, u32Data)  ((i2s)->TX = (u32Data))  argument
540 #define SPII2S_READ_RX_FIFO(i2s) ((i2s)->RX)  argument
550 #define SPII2S_GET_INT_FLAG(i2s, u32Mask) ((i2s)->I2SSTS & (u32Mask))  argument
561 #define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ((i2s)->I2SSTS = (u32Mask))  argument
570 #define SPII2S_GET_TX_FIFO_LEVEL(i2s) (((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_P…  argument
579 #define SPII2S_GET_RX_FIFO_LEVEL(i2s) (((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_P…  argument
597 uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordW…
598 void SPII2S_Close(SPI_T *i2s);
599 void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
600 void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
601 uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
602 void SPII2S_DisableMCLK(SPI_T *i2s);
603 void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);