Lines Matching refs:SPI_T

352 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
353 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask);
354 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch);
365 __STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)  in SPII2S_ENABLE_TX_ZCD()
386 __STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)  in SPII2S_DISABLE_TX_ZCD()
516 __STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)  in SPII2S_SET_MONO_RX_CHANNEL()
582 uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, …
583 void SPI_Close(SPI_T *spi);
584 void SPI_ClearRxFIFO(SPI_T *spi);
585 void SPI_ClearTxFIFO(SPI_T *spi);
586 void SPI_DisableAutoSS(SPI_T *spi);
587 void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
588 uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
589 void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
590 uint32_t SPI_GetBusClock(SPI_T *spi);
591 void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
592 void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
593 uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
594 void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
595 uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
597 uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordW…
598 void SPII2S_Close(SPI_T *i2s);
599 void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
600 void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
601 uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
602 void SPII2S_DisableMCLK(SPI_T *i2s);
603 void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);