204 MSS_TIM1_init(TIMER_TypeDef* timer, mss_timer_mode_t mode)  in MSS_TIM1_init()  argument
208     timer->TIM64_MODE = 0u;                     /* switch to 32 bits mode */  in MSS_TIM1_init()
209     readvalue[1] = timer->TIM64_MODE;  in MSS_TIM1_init()
212     timer->TIM1_CTRL = TIM1_MODE_MASK & ((uint32_t)mode << TIM1_MODE_SHIFT);  in MSS_TIM1_init()
213     readvalue[2] = timer->TIM1_CTRL;  in MSS_TIM1_init()
215     timer->TIM1_RIS = 1u;                       /* clear timer 1 interrupt */  in MSS_TIM1_init()
216     readvalue[3] = timer->TIM1_RIS;  in MSS_TIM1_init()
231 MSS_TIM1_start(TIMER_TypeDef* timer)  in MSS_TIM1_start()  argument
233     timer->TIM1_CTRL |= TIM1_ENABLE_MASK;  in MSS_TIM1_start()
245 MSS_TIM1_stop(TIMER_TypeDef* timer)  in MSS_TIM1_stop()  argument
247     timer->TIM1_CTRL &= ~((uint32_t)TIM1_ENABLE_MASK);    /* disable timer */  in MSS_TIM1_stop()
261 MSS_TIM1_get_current_value(TIMER_TypeDef* timer)  in MSS_TIM1_get_current_value()  argument
263     return timer->TIM1_VAL;  in MSS_TIM1_get_current_value()
286 MSS_TIM1_load_immediate(TIMER_TypeDef* timer, uint32_t load_value)  in MSS_TIM1_load_immediate()  argument
288     timer->TIM1_LOADVAL = load_value;  in MSS_TIM1_load_immediate()
308 MSS_TIM1_load_background(TIMER_TypeDef* timer, uint32_t load_value)  in MSS_TIM1_load_background()  argument
310     timer->TIM1_BGLOADVAL = load_value;  in MSS_TIM1_load_background()
328 MSS_TIM1_enable_irq(TIMER_TypeDef* timer)  in MSS_TIM1_enable_irq()  argument
330     timer->TIM1_CTRL |= TIM1_INTEN_MASK;  in MSS_TIM1_enable_irq()
331     readvalue[8] = timer->TIM1_CTRL;  in MSS_TIM1_enable_irq()
344 MSS_TIM1_disable_irq(TIMER_TypeDef* timer)  in MSS_TIM1_disable_irq()  argument
346     timer->TIM1_CTRL &= ~((uint32_t)TIM1_INTEN_MASK);  in MSS_TIM1_disable_irq()
364 MSS_TIM1_clear_irq(TIMER_TypeDef* timer)  in MSS_TIM1_clear_irq()  argument
366     timer->TIM1_RIS = 1u;  in MSS_TIM1_clear_irq()
390 MSS_TIM2_init(TIMER_TypeDef* timer, mss_timer_mode_t mode)  in MSS_TIM2_init()  argument
393     timer->TIM64_MODE = 0u;                     /* switch to 32 bits mode */  in MSS_TIM2_init()
396     timer->TIM2_CTRL = TIM2_MODE_MASK & ((uint32_t)mode << TIM2_MODE_SHIFT);  in MSS_TIM2_init()
398     timer->TIM2_RIS = 1u;                       /* clear timer 2 interrupt */  in MSS_TIM2_init()
413 MSS_TIM2_start(TIMER_TypeDef* timer)  in MSS_TIM2_start()  argument
415     timer->TIM2_CTRL |= TIM2_ENABLE_MASK;     /* enable timer */  in MSS_TIM2_start()
426 MSS_TIM2_stop(TIMER_TypeDef* timer)  in MSS_TIM2_stop()  argument
428     timer->TIM2_CTRL &= ~((uint32_t)TIM2_ENABLE_MASK);    /* disable timer */  in MSS_TIM2_stop()
439 MSS_TIM2_get_current_value(TIMER_TypeDef* timer)  in MSS_TIM2_get_current_value()  argument
441     return timer->TIM2_VAL;  in MSS_TIM2_get_current_value()
464 MSS_TIM2_load_immediate(TIMER_TypeDef* timer, uint32_t load_value)  in MSS_TIM2_load_immediate()  argument
466     timer->TIM2_LOADVAL = load_value;  in MSS_TIM2_load_immediate()
486 MSS_TIM2_load_background(TIMER_TypeDef* timer, uint32_t load_value)  in MSS_TIM2_load_background()  argument
488     timer->TIM2_BGLOADVAL = load_value;  in MSS_TIM2_load_background()
505 MSS_TIM2_enable_irq(TIMER_TypeDef* timer)  in MSS_TIM2_enable_irq()  argument
507     timer->TIM2_CTRL |= TIM2_INTEN_MASK;  in MSS_TIM2_enable_irq()
519 MSS_TIM2_disable_irq(TIMER_TypeDef* timer)  in MSS_TIM2_disable_irq()  argument
521     timer->TIM2_CTRL &=  ~((uint32_t)TIM2_INTEN_MASK);  in MSS_TIM2_disable_irq()
539 MSS_TIM2_clear_irq(TIMER_TypeDef* timer)  in MSS_TIM2_clear_irq()  argument
541     timer->TIM2_RIS = 1u;  in MSS_TIM2_clear_irq()
565 MSS_TIM64_init(TIMER_TypeDef* timer, mss_timer_mode_t mode)  in MSS_TIM64_init()  argument
570     timer->TIM64_MODE = 1u;                     /* switch to 64 bits mode */  in MSS_TIM64_init()
573     timer->TIM64_CTRL = TIM64_MODE_MASK & ((uint32_t)mode << TIM64_MODE_SHIFT);  in MSS_TIM64_init()
575     timer->TIM1_RIS = 1u;                   /* clear timer 1 interrupt */  in MSS_TIM64_init()
576     timer->TIM2_RIS = 1u;                   /* clear timer 2 interrupt */  in MSS_TIM64_init()
591 MSS_TIM64_start(TIMER_TypeDef* timer)  in MSS_TIM64_start()  argument
593     timer->TIM64_CTRL |= TIM64_ENABLE_MASK;   /* enable timer */  in MSS_TIM64_start()
604 MSS_TIM64_stop(TIMER_TypeDef* timer)  in MSS_TIM64_stop()  argument
606     timer->TIM64_CTRL &= ~((uint32_t)TIM64_ENABLE_MASK);    /* disable timer */  in MSS_TIM64_stop()
634     TIMER_TypeDef* timer,  in MSS_TIM64_get_current_value()  argument
639     *load_value_l = timer->TIM64_VAL_L;  in MSS_TIM64_get_current_value()
640     *load_value_u = timer->TIM64_VAL_U;  in MSS_TIM64_get_current_value()
670     TIMER_TypeDef* timer,  in MSS_TIM64_load_immediate()  argument
675     timer->TIM64_LOADVAL_U = load_value_u;  in MSS_TIM64_load_immediate()
676     timer->TIM64_LOADVAL_L = load_value_l;  in MSS_TIM64_load_immediate()
708     TIMER_TypeDef* timer,  in MSS_TIM64_load_background()  argument
713     timer->TIM64_BGLOADVAL_U = load_value_u;  in MSS_TIM64_load_background()
714     timer->TIM64_BGLOADVAL_L = load_value_l;  in MSS_TIM64_load_background()
736 MSS_TIM64_enable_irq(TIMER_TypeDef* timer)  in MSS_TIM64_enable_irq()  argument
738     timer->TIM64_CTRL |= TIM64_INTEN_MASK;  in MSS_TIM64_enable_irq()
751 MSS_TIM64_disable_irq(TIMER_TypeDef* timer)  in MSS_TIM64_disable_irq()  argument
753     timer->TIM64_CTRL &= ~((uint32_t)TIM64_INTEN_MASK);  in MSS_TIM64_disable_irq()
770 MSS_TIM64_clear_irq(TIMER_TypeDef* timer)  in MSS_TIM64_clear_irq()  argument
772     timer->TIM64_RIS = 1u;  in MSS_TIM64_clear_irq()