Lines Matching refs:EFUSE_BLK0
3 # | (EFUSE_BLK0 | (0..255) | (1-256) | #
14 WR_DIS, EFUSE_BLK0, 0, 16, [] Efuse write disable mask
15 WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [WR_DIS.EFUSE_RD_DISABLE] wr…
16 WR_DIS.WR_DIS, EFUSE_BLK0, 1, 1, [] wr_dis of WR_DIS
17 WR_DIS.FLASH_CRYPT_CNT, EFUSE_BLK0, 2, 1, [] wr_dis of FLASH_CRYPT_CNT
18 WR_DIS.UART_DOWNLOAD_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of UART_DOWNLOAD_D…
19 WR_DIS.MAC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY] wr_dis …
20 WR_DIS.MAC_CRC, EFUSE_BLK0, 3, 1, [WR_DIS.MAC_FACTORY_CRC] wr_…
21 WR_DIS.DISABLE_APP_CPU, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_APP_CPU…
22 WR_DIS.DISABLE_BT, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_BT] wr_…
23 WR_DIS.DIS_CACHE, EFUSE_BLK0, 3, 1, [WR_DIS.CHIP_VER_DIS_CACHE] …
24 WR_DIS.VOL_LEVEL_HP_INV, EFUSE_BLK0, 3, 1, [] wr_dis of VOL_LEVEL_HP_INV
25 WR_DIS.CLK8M_FREQ, EFUSE_BLK0, 4, 1, [WR_DIS.CK8M_FREQ] wr_dis of…
26 WR_DIS.ADC_VREF, EFUSE_BLK0, 4, 1, [] wr_dis of ADC_VREF
27 WR_DIS.XPD_SDIO_REG, EFUSE_BLK0, 5, 1, [] wr_dis of XPD_SDIO_REG
28 WR_DIS.XPD_SDIO_TIEH, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_TIEH] wr_dis of…
29 WR_DIS.XPD_SDIO_FORCE, EFUSE_BLK0, 5, 1, [WR_DIS.SDIO_FORCE] wr_dis o…
30 WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_…
31 WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_Q
32 WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_D
33 WR_DIS.SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 6, 1, [] wr_dis of SPI_PAD_CONFIG_…
34 WR_DIS.BLOCK1, EFUSE_BLK0, 7, 1, [WR_DIS.ENCRYPT_FLASH_KEY WR…
35 WR_DIS.BLOCK2, EFUSE_BLK0, 8, 1, [WR_DIS.SECURE_BOOT_KEY WR_D…
36 WR_DIS.BLOCK3, EFUSE_BLK0, 9, 1, [WR_DIS.BLK3] wr_dis of BLOC…
37 WR_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_CRC] wr_d…
38 WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM] wr_dis o…
39 WR_DIS.ADC1_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_LOW
40 WR_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC1_TP_HIGH
41 WR_DIS.ADC2_TP_LOW, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_LOW
42 WR_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 9, 1, [] wr_dis of ADC2_TP_HIGH
43 WR_DIS.SECURE_VERSION, EFUSE_BLK0, 9, 1, [] wr_dis of SECURE_VERSION
44 WR_DIS.MAC_VERSION, EFUSE_BLK0, 9, 1, [WR_DIS.MAC_CUSTOM_VER] wr_d…
45 WR_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 10, 1, [] wr_dis of BLK3_PART_RESER…
46 WR_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 10, 1, [WR_DIS.ENCRYPT_CONFIG] wr_d…
47 WR_DIS.CODING_SCHEME, EFUSE_BLK0, 10, 1, [] wr_dis of CODING_SCHEME
48 WR_DIS.KEY_STATUS, EFUSE_BLK0, 10, 1, [] wr_dis of KEY_STATUS
49 WR_DIS.ABS_DONE_0, EFUSE_BLK0, 12, 1, [] wr_dis of ABS_DONE_0
50 WR_DIS.ABS_DONE_1, EFUSE_BLK0, 13, 1, [] wr_dis of ABS_DONE_1
51 WR_DIS.JTAG_DISABLE, EFUSE_BLK0, 14, 1, [WR_DIS.DISABLE_JTAG] wr_dis…
52 WR_DIS.CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 15, 1, [] wr_dis of CONSOLE_DEBUG_D…
53 WR_DIS.DISABLE_DL_ENCRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_ENCR…
54 WR_DIS.DISABLE_DL_DECRYPT, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_DECR…
55 WR_DIS.DISABLE_DL_CACHE, EFUSE_BLK0, 15, 1, [] wr_dis of DISABLE_DL_CACHE
56 RD_DIS, EFUSE_BLK0, 16, 4, [] Disable reading from BlOC…
57 RD_DIS.BLOCK1, EFUSE_BLK0, 16, 1, [RD_DIS.ENCRYPT_FLASH_KEY RD…
58 RD_DIS.BLOCK2, EFUSE_BLK0, 17, 1, [RD_DIS.SECURE_BOOT_KEY RD_D…
59 RD_DIS.BLOCK3, EFUSE_BLK0, 18, 1, [RD_DIS.BLK3] rd_dis of BLOC…
60 RD_DIS.CUSTOM_MAC_CRC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_CRC] rd_d…
61 RD_DIS.CUSTOM_MAC, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM] rd_dis o…
62 RD_DIS.ADC1_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_LOW
63 RD_DIS.ADC1_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC1_TP_HIGH
64 RD_DIS.ADC2_TP_LOW, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_LOW
65 RD_DIS.ADC2_TP_HIGH, EFUSE_BLK0, 18, 1, [] rd_dis of ADC2_TP_HIGH
66 RD_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] rd_dis of SECURE_VERSION
67 RD_DIS.MAC_VERSION, EFUSE_BLK0, 18, 1, [RD_DIS.MAC_CUSTOM_VER] rd_d…
68 RD_DIS.BLK3_PART_RESERVE, EFUSE_BLK0, 19, 1, [] rd_dis of BLK3_PART_RESER…
69 RD_DIS.FLASH_CRYPT_CONFIG, EFUSE_BLK0, 19, 1, [RD_DIS.ENCRYPT_CONFIG] rd_d…
70 RD_DIS.CODING_SCHEME, EFUSE_BLK0, 19, 1, [] rd_dis of CODING_SCHEME
71 RD_DIS.KEY_STATUS, EFUSE_BLK0, 19, 1, [] rd_dis of KEY_STATUS
72 FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, [] Flash encryption is enabl…
73 UART_DOWNLOAD_DIS, EFUSE_BLK0, 27, 1, [] Disable UART download mod…
74 MAC, EFUSE_BLK0, 72, 8, [MAC_FACTORY] MAC address
75 , EFUSE_BLK0, 64, 8, [MAC_FACTORY] MAC address
76 , EFUSE_BLK0, 56, 8, [MAC_FACTORY] MAC address
77 , EFUSE_BLK0, 48, 8, [MAC_FACTORY] MAC address
78 , EFUSE_BLK0, 40, 8, [MAC_FACTORY] MAC address
79 , EFUSE_BLK0, 32, 8, [MAC_FACTORY] MAC address
80 MAC_CRC, EFUSE_BLK0, 80, 8, [MAC_FACTORY_CRC] CRC8 for M…
81 DISABLE_APP_CPU, EFUSE_BLK0, 96, 1, [CHIP_VER_DIS_APP_CPU] Disab…
82 DISABLE_BT, EFUSE_BLK0, 97, 1, [CHIP_VER_DIS_BT] Disables B…
83 CHIP_PACKAGE_4BIT, EFUSE_BLK0, 98, 1, [CHIP_VER_PKG_4BIT] Chip pac…
84 DIS_CACHE, EFUSE_BLK0, 99, 1, [CHIP_VER_DIS_CACHE] Disable…
85 SPI_PAD_CONFIG_HD, EFUSE_BLK0, 100, 5, [] read for SPI_pad_config_hd
86 CHIP_PACKAGE, EFUSE_BLK0, 105, 3, [CHIP_VER_PKG] Chip package …
87 CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, [] If set alongside EFUSE_RD…
88 CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, [] If set; the ESP32's maxim…
89 BLK3_PART_RESERVE, EFUSE_BLK0, 110, 1, [] BLOCK3 partially served f…
90 CHIP_VER_REV1, EFUSE_BLK0, 111, 1, [] bit is set to 1 for rev1 …
91 CLK8M_FREQ, EFUSE_BLK0, 128, 8, [CK8M_FREQ] 8MHz clock freq …
92 ADC_VREF, EFUSE_BLK0, 136, 5, [] True ADC reference voltage
93 XPD_SDIO_REG, EFUSE_BLK0, 142, 1, [] read for XPD_SDIO_REG
94 XPD_SDIO_TIEH, EFUSE_BLK0, 143, 1, [SDIO_TIEH] If XPD_SDIO_FORC…
95 XPD_SDIO_FORCE, EFUSE_BLK0, 144, 1, [SDIO_FORCE] Ignore MTDI pin…
96 SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 160, 5, [] Override SD_CLK pad (GPIO…
97 SPI_PAD_CONFIG_Q, EFUSE_BLK0, 165, 5, [] Override SD_DATA_0 pad (G…
98 SPI_PAD_CONFIG_D, EFUSE_BLK0, 170, 5, [] Override SD_DATA_1 pad (G…
99 SPI_PAD_CONFIG_CS0, EFUSE_BLK0, 175, 5, [] Override SD_CMD pad (GPIO…
100 CHIP_VER_REV2, EFUSE_BLK0, 180, 1, []
101 VOL_LEVEL_HP_INV, EFUSE_BLK0, 182, 2, [] This field stores the vol…
102 WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, []
103 FLASH_CRYPT_CONFIG, EFUSE_BLK0, 188, 4, [ENCRYPT_CONFIG] Flash encry…
104 CODING_SCHEME, EFUSE_BLK0, 192, 2, [] Efuse variable block leng…
105 CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, [] Disable ROM BASIC interpr…
106 DISABLE_SDIO_HOST, EFUSE_BLK0, 195, 1, []
107 ABS_DONE_0, EFUSE_BLK0, 196, 1, [] Secure boot V1 is enabled…
108 ABS_DONE_1, EFUSE_BLK0, 197, 1, [] Secure boot V2 is enabled…
109 JTAG_DISABLE, EFUSE_BLK0, 198, 1, [DISABLE_JTAG] Disable JTAG
110 DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, [] Disable flash encryption …
111 DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, [] Disable flash decryption …
112 DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, [] Disable flash cache in UA…
113 KEY_STATUS, EFUSE_BLK0, 202, 1, [] Usage of efuse block 3 (r…