Lines Matching +full:all +full:- +full:inputs
4 * SPDX-License-Identifier: Apache-2.0
17 * inputs.
26 ECS_REGS->INTR_CTRL |= MCHP_ECS_ICTRL_DIRECT_EN; in soc_ecia_init()
28 /* gate off all aggregated outputs */ in soc_ecia_init()
29 ECIA_REGS->BLK_EN_CLR = 0xFFFFFFFFul; in soc_ecia_init()
31 ECIA_REGS->BLK_EN_SET = MCHP_ECIA_AGGR_BITMAP; in soc_ecia_init()
33 /* Clear all GIRQn source enables and source status */ in soc_ecia_init()
34 pg = &ECIA_REGS->GIRQ08; in soc_ecia_init()
36 pg->EN_CLR = 0xFFFFFFFFul; in soc_ecia_init()
37 pg->SRC = 0xFFFFFFFFul; in soc_ecia_init()
41 /* Clear all external NVIC enables and pending status */ in soc_ecia_init()
43 NVIC->ICER[n] = 0xFFFFFFFFul; in soc_ecia_init()
44 NVIC->ICPR[n] = 0xFFFFFFFFul; in soc_ecia_init()
53 ECS_REGS->DEBUG_CTRL = 0; in configure_debug_interface()
54 ECS_REGS->ETM_CTRL = 0; in configure_debug_interface()
59 * For more details see table 44-1 in configure_debug_interface()
61 ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | in configure_debug_interface()
67 ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | in configure_debug_interface()
89 ECS_REGS->GPIO_BANK_PWR |= MCHP_ECS_VTR3_LVL_18; in soc_early_init_hook()