Lines Matching +full:- +full:- +full:can +full:- +full:if
2 # SPDX-License-Identifier: Apache-2.0
4 if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
7 bool "Support for external, SPI-connected RAM"
8 default n if MCUBOOT
9 default n if ESP32_USE_UNSUPPORTED_REVISION && SOC_SERIES_ESP32
23 regions. If the region of desired capability is exhausted,
28 default 262134 if SYS_HEAP_SMALL_ONLY
29 default 1048576 if !SYS_HEAP_SMALL_ONLY
54 default SPIRAM_TYPE_ESPPSRAM16 if SPIRAM_MODE_QUAD
58 bool "ESP-PSRAM16 or APS1604"
62 bool "ESP-PSRAM32 or IS25WP032"
66 bool "ESP-PSRAM64, LY68L6400 or APS6408"
72 default 2097152 if SPIRAM_TYPE_ESPPSRAM16
73 default 4194304 if SPIRAM_TYPE_ESPPSRAM32
74 default 8388608 if SPIRAM_TYPE_ESPPSRAM64
77 NOTE: If SPIRAM size is greater than 4MB, only
78 lower 4MB can be allocated using k_malloc().
109 default 120 if SPIRAM_SPEED_120M
110 default 80 if SPIRAM_SPEED_80M
111 default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M
128 If enabled, instructions in flash will be moved into PSRAM on startup.
129 If SPIRAM_RODATA is also enabled, code that requires execution during an SPI1 Flash operation
130 can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
134 bool "Move Read-Only Data in Flash to PSRAM"
138 If enabled, rodata in flash will be moved into PSRAM on startup.
139 …If SPIRAM_FETCH_INSTRUCTIONS is also enabled, code that requires execution during an SPI1 Flash op…
140 can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
148 Enable MSPI Error-Correcting Code function when accessing SPIRAM.
149 If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
151 if SOC_SERIES_ESP32
153 menu "PSRAM clock and cs IO for ESP32-DOWD"
160 …The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
161 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
168 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
169 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
171 endmenu # PSRAM clock and cs IO for ESP32-DOWD
173 menu "PSRAM clock and cs IO for ESP32-D2WD"
180 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
181 so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
188 …User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
189 so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
191 endmenu # PSRAM clock and cs IO for ESP32-D2WD
193 menu "PSRAM clock and cs IO for ESP32-PICO"
200 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
202 For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
204 https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
206 endmenu # PSRAM clock and cs IO for ESP32-PICO
213 This setting is only used if the SPI flash pins have been overridden by setting the eFuses
220 If this config item is set to N (default), the correct WP pin will be automatically used for any
221 …Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
235 …If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set t…