Lines Matching +full:main +full:- +full:mode

2  * Copyright (c) 2013-2015 Wind River Systems, Inc.
6  * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
8  * SPDX-License-Identifier: Apache-2.0
15  * This module provides routines to initialize and support board-level hardware
28  * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
33 	/* Switch the main clock to the internal OSC with 12MHz */  in clock_init()
36 	/* Switch MCK (Master Clock) to the main clock */  in clock_init()
39 	EFC0->EEFC_FMR = EEFC_FMR_FWS(0);  in clock_init()
41 	EFC1->EEFC_FMR = EEFC_FMR_FWS(0);  in clock_init()
52 		 * Setup main external crystal oscillator.  in clock_init()
71 	EFC0->EEFC_FMR = EEFC_FMR_FWS(5);  in clock_init()
73 	EFC1->EEFC_FMR = EEFC_FMR_FWS(5);  in clock_init()
102 		 * Instruct CPU to enter Wait mode instead of Sleep mode to  in soc_reset_hook()