Lines Matching +full:0 +full:xb9

20 #define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
24 #define SPI_NOR_CMD_WRSR 0x01 /* Write status register */
25 #define SPI_NOR_CMD_RDSR 0x05 /* Read status register */
26 #define SPI_NOR_CMD_READ 0x03 /* Read data */
27 #define SPI_NOR_CMD_WREN 0x06 /* Write enable */
28 #define SPI_NOR_CMD_WRDI 0x04 /* Write disable */
29 #define SPI_NOR_CMD_PP 0x02 /* Page program */
30 #define SPI_NOR_CMD_SE 0x20 /* Sector erase */
31 #define SPI_NOR_CMD_BE_32K 0x52 /* Block erase 32KB */
32 #define SPI_NOR_CMD_BE 0xD8 /* Block erase */
33 #define SPI_NOR_CMD_CE 0xC7 /* Chip erase */
34 #define SPI_NOR_CMD_RDID 0x9F /* Read JEDEC ID */
35 #define SPI_NOR_CMD_ULBPR 0x98 /* Global Block Protection Unlock */
36 #define SPI_NOR_CMD_4BA 0xB7 /* Enter 4-Byte Address Mode */
37 #define SPI_NOR_CMD_DPD 0xB9 /* Deep Power Down */
38 #define SPI_NOR_CMD_RDPD 0xAB /* Release from Deep Power Down */
41 #define SPI_NOR_PAGE_SIZE 0x0100U
42 #define SPI_NOR_SECTOR_SIZE 0x1000U
43 #define SPI_NOR_BLOCK_SIZE 0x10000U
46 #define SPI_NOR_IS_ALIGNED(_ofs, _bits) (((_ofs)&BIT_MASK(_bits)) == 0)