Lines Matching full:level

10 #define WIFI_MAC_INTR_SOURCE                0  /* interrupt of WiFi MAC, level*/
13 #define WIFI_BB_INTR_SOURCE                 3  /* interrupt of WiFi BB, level*/
15 #define BT_BB_INTR_SOURCE                   5  /* interrupt of BT BB, level*/
21 #define I2C_MASTER_SOURCE                  11  /* interrupt of I2C Master, level*/
24 #define EFUSE_INTR_SOURCE                  14  /* interrupt of efuse, level, not likely to use*/
32 #define FROM_CPU_INTR0_SOURCE              22  /* interrupt0 generated from a CPU, level*/
33 #define FROM_CPU_INTR1_SOURCE              23  /* interrupt1 generated from a CPU, level*/
34 #define FROM_CPU_INTR2_SOURCE              24  /* interrupt2 generated from a CPU, level*/
35 #define FROM_CPU_INTR3_SOURCE              25  /* interrupt3 generated from a CPU, level*/
36 #define ASSIST_DEBUG_INTR_SOURCE           26  /* interrupt of Assist debug module, LEVEL*/
40 #define GPIO_INTR_SOURCE                   30  /* interrupt of GPIO, level*/
51 #define I2S1_INTR_SOURCE                   41  /* interrupt of I2S1, level*/
52 #define UHCI0_INTR_SOURCE                  42  /* interrupt of UHCI0, level*/
53 #define UART0_INTR_SOURCE                  43  /* interrupt of UART0, level*/
54 #define UART1_INTR_SOURCE                  44  /* interrupt of UART1, level*/
55 #define LEDC_INTR_SOURCE                   45  /* interrupt of LED PWM, level*/
56 #define TWAI0_INTR_SOURCE                  46  /* interrupt of can0, level*/
57 #define TWAI1_INTR_SOURCE                  47  /* interrupt of can1, level*/
58 #define USB_SERIAL_JTAG_INTR_SOURCE        48  /* interrupt of USB, level*/
59 #define RMT_INTR_SOURCE                    49  /* interrupt of remote controller, level*/
60 #define I2C_EXT0_INTR_SOURCE               50  /* interrupt of I2C controller1, level*/
61 #define TG0_T0_LEVEL_INTR_SOURCE           51  /* interrupt of TIMER_GROUP0, TIMER0, level*/
62 #define TG0_T1_LEVEL_INTR_SOURCE           52  /* interrupt of TIMER_GROUP0, TIMER1, level*/
63 #define TG0_WDT_LEVEL_INTR_SOURCE          53  /* interrupt of TIMER_GROUP0, WATCH DOG, level*/
64 #define TG1_T0_LEVEL_INTR_SOURCE           54  /* interrupt of TIMER_GROUP1, TIMER0, level*/
65 #define TG1_T1_LEVEL_INTR_SOURCE           55  /* interrupt of TIMER_GROUP1, TIMER1, level*/
66 #define TG1_WDT_LEVEL_INTR_SOURCE          56  /* interrupt of TIMER_GROUP1, WATCHDOG, level*/
70 #define APB_ADC_INTR_SOURCE                60  /* interrupt of APB ADC, LEVEL*/
71 #define MCPWM0_INTR_SOURCE                 61  /* interrupt of MCPWM0, LEVEL*/
76 #define DMA_IN_CH0_INTR_SOURCE             66  /* interrupt of general DMA IN channel 0, LEVEL*/
77 #define DMA_IN_CH1_INTR_SOURCE             67  /* interrupt of general DMA IN channel 1, LEVEL*/
78 #define DMA_IN_CH2_INTR_SOURCE             68  /* interrupt of general DMA IN channel 2, LEVEL*/
79 #define DMA_OUT_CH0_INTR_SOURCE            69  /* interrupt of general DMA OUT channel 0, LEVEL*/
80 #define DMA_OUT_CH1_INTR_SOURCE            70  /* interrupt of general DMA OUT channel 1, LEVEL*/
81 #define DMA_OUT_CH2_INTR_SOURCE            71  /* interrupt of general DMA OUT channel 2, LEVEL*/
83 #define AES_INTR_SOURCE                    73  /* interrupt of AES accelerator, level*/
84 #define SHA_INTR_SOURCE                    74  /* interrupt of SHA accelerator, level*/
85 #define RSA_INTR_SOURCE                    75  /* interrupt of RSA accelerator, level*/
86 #define ECC_INTR_SOURCE                    76  /* interrupt of ECC accelerator, level*/