Lines Matching +full:vendor +full:- +full:id
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "intel,alder-lake", "intel,x86_64";
22 d-cache-line-size = <64>;
28 compatible = "intel,alder-lake";
29 d-cache-line-size = <64>;
42 #address-cells = <1>;
43 #interrupt-cells = <3>;
45 interrupt-controller;
51 interrupt-controller;
52 #interrupt-cells = <3>;
53 #address-cells = <1>;
58 acpi-hid = "INTC1057";
59 acpi-uid = "2";
60 group-index = <0x02>;
65 acpi-hid = "INTC1057";
66 acpi-uid = "0";
67 group-index = <0x0>;
72 acpi-hid = "INTC1057";
73 acpi-uid = "0";
74 group-index = <0x0B>;
79 acpi-hid = "INTC1057";
80 acpi-uid = "0";
81 group-index = <0x8>;
86 acpi-hid = "INTC1057";
87 acpi-uid = "0";
88 group-index = <0xE>;
93 acpi-hid = "INTC1057";
94 acpi-uid = "0";
95 group-index = <0xC>;
100 acpi-hid = "INTC1057";
101 acpi-uid = "0";
102 group-index = <0x7>;
107 acpi-hid = "INTC1057";
108 acpi-uid = "0";
109 group-index = <0x9>;
114 acpi-hid = "INTC1057";
115 acpi-uid = "0";
116 group-index = <0x6>;
121 acpi-hid = "INTC1057";
122 acpi-uid = "0";
123 group-index = <0x3>;
128 acpi-hid = "INTC1057";
129 acpi-uid = "0";
130 group-index = <0x1>;
135 acpi-hid = "INTC1057";
136 acpi-uid = "0";
137 group-index = <0xA>;
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "pcie-controller";
146 acpi-hid = "PNP0A08";
150 compatible = "intel,pch-smbus";
151 #address-cells = <1>;
152 #size-cells = <0>;
153 vendor-id = <0x8086>;
154 device-id = <0x54a3>;
156 interrupt-parent = <&intc>;
164 vendor-id = <0x8086>;
165 device-id = <0x54a8>;
167 clock-frequency = <1843200>;
168 current-speed = <115200>;
169 reg-shift = <2>;
172 interrupt-parent = <&intc>;
178 #dma-cells = <1>;
184 vendor-id = <0x8086>;
185 device-id = <0x54A9>;
186 clock-frequency = <1843200>;
187 current-speed = <115200>;
188 reg-shift = <2>;
190 interrupt-parent = <&intc>;
192 dma-names = "tx", "rx";
198 #dma-cells = <1>;
204 vendor-id = <0x8086>;
205 device-id = <0x54C7>;
206 clock-frequency = <1843200>;
207 current-speed = <115200>;
208 reg-shift = <2>;
210 interrupt-parent = <&intc>;
212 dma-names = "tx", "rx";
218 compatible = "snps,designware-i2c";
219 clock-frequency = <I2C_BITRATE_STANDARD>;
220 #address-cells = <1>;
221 #size-cells = <0>;
222 vendor-id = <0x8086>;
223 device-id = <0x54e8>;
225 interrupt-parent = <&intc>;
231 compatible = "snps,designware-i2c";
232 clock-frequency = <I2C_BITRATE_STANDARD>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 vendor-id = <0x8086>;
236 device-id = <0x54e9>;
238 interrupt-parent = <&intc>;
244 compatible = "snps,designware-i2c";
245 clock-frequency = <I2C_BITRATE_STANDARD>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 vendor-id = <0x8086>;
249 device-id = <0x54ea>;
251 interrupt-parent = <&intc>;
257 compatible = "snps,designware-i2c";
258 clock-frequency = <I2C_BITRATE_STANDARD>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 vendor-id = <0x8086>;
262 device-id = <0x54eb>;
264 interrupt-parent = <&intc>;
270 compatible = "snps,designware-i2c";
271 clock-frequency = <I2C_BITRATE_STANDARD>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 vendor-id = <0x8086>;
275 device-id = <0x54c5>;
277 interrupt-parent = <&intc>;
283 compatible = "snps,designware-i2c";
284 clock-frequency = <I2C_BITRATE_STANDARD>;
285 #address-cells = <1>;
286 #size-cells = <0>;
287 vendor-id = <0x8086>;
288 device-id = <0x54c6>;
290 interrupt-parent = <&intc>;
296 compatible = "intel,penwell-spi";
297 vendor-id = <0x8086>;
298 device-id = <0x54aa>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 pw,cs-mode = <0>;
302 pw,cs-output = <0>;
303 pw,fifo-depth = <64>;
304 cs-gpios = <&gpio_e 10 GPIO_ACTIVE_LOW>;
305 clock-frequency = <100000000>;
307 interrupt-parent = <&intc>;
312 compatible = "intel,penwell-spi";
313 vendor-id = <0x8086>;
314 device-id = <0x54ab>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 pw,cs-mode = <0>;
318 pw,cs-output = <0>;
319 pw,fifo-depth = <64>;
320 cs-gpios = <&gpio_f 16 GPIO_ACTIVE_LOW>;
321 clock-frequency = <100000000>;
323 interrupt-parent = <&intc>;
328 compatible = "intel,penwell-spi";
329 vendor-id = <0x8086>;
330 device-id = <0x54fb>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 pw,cs-mode = <0>;
334 pw,cs-output = <0>;
335 pw,fifo-depth = <64>;
336 cs-gpios = <&gpio_d 9 GPIO_ACTIVE_LOW>;
337 clock-frequency = <100000000>;
339 interrupt-parent = <&intc>;
344 compatible = "intel,emmc-host";
345 vendor-id = <0x8086>;
346 device-id = <0x54C4>;
348 interrupt-parent = <&intc>;
350 max-bus-freq = <200000000>;
351 min-bus-freq = <400000>;
352 power-delay-ms = <500>;
353 mmc-hs400-1_8v;
354 mmc-hs200-1_8v;
357 compatible = "zephyr,mmc-disk";
358 disk-name = "SD2";
359 bus-width = <8>;
368 #address-cells = <1>;
369 #size-cells = <1>;
370 compatible = "simple-bus";
374 compatible = "intel,vt-d";
382 io-mapped;
383 clock-frequency = <1843200>;
385 interrupt-parent = <&intc>;
386 reg-shift = <0>;
391 compatible = "intel,timeaware-gpio";
393 timer-clock = <19200000>;
394 max-pins = <2>;
402 interrupt-parent = <&intc>;
411 interrupt-parent = <&intc>;
412 alarms-count = <1>;
418 compatible = "intel,tco-wdt";
424 compatible = "intel,blinky-pwm";
426 reg-offset = <0x204>;
427 clock-frequency = <32768>;
428 max-pins = <1>;
429 #pwm-cells = <2>;