Lines Matching full:litex

12 	compatible = "litex,vexriscv", "litex-dev";
13 	model = "litex,vexriscv";
25 			compatible = "litex,vexriscv-standard", "riscv";
35 		compatible = "litex,vexriscv";
38 			compatible = "litex,soc-controller";
47 			compatible = "litex,vexriscv-intc0";
56 			compatible = "litex,uart";
79 			compatible = "litex,spi";
97 			compatible = "litex,spi-litespi";
121 			compatible = "litex,timer0";
148 			compatible = "litex,watchdog";
165 			compatible = "litex,liteeth-mdio";
182 			compatible = "litex,liteeth";
220 			compatible = "litex,dna0";
223 			In LiteX each 32-bit register holds
231 			compatible = "litex,i2c";
240 			compatible = "litex,gpio";
250 			compatible = "litex,gpio";
269 			compatible = "litex,prbs";
275 			compatible = "litex,pwm";
282 			compatible = "litex,i2s";
305 			compatible = "litex,i2s";
333 				compatible = "litex,clkout";
335 				litex,clock-frequency = <11289600>;
336 				litex,clock-phase = <0>;
337 				litex,clock-duty-num = <1>;
338 				litex,clock-duty-den = <2>;
339 				litex,clock-margin = <1>;
340 				litex,clock-margin-exp = <2>;
346 				compatible = "litex,clkout";
348 				litex,clock-frequency = <22579200>;
349 				litex,clock-phase = <0>;
350 				litex,clock-duty-num = <1>;
351 				litex,clock-duty-den = <2>;
352 				litex,clock-margin = <1>;
353 				litex,clock-margin-exp = <2>;
358 			compatible = "litex,clk";
378 			litex,lock-timeout = <10>;
379 			litex,drdy-timeout = <10>;
380 			litex,divclk-divide-min = <1>;
381 			litex,divclk-divide-max = <107>;
382 			litex,clkfbout-mult-min = <2>;
383 			litex,clkfbout-mult-max = <65>;
384 			litex,vco-freq-min = <600000000>;
385 			litex,vco-freq-max = <1200000000>;
386 			litex,clkout-divide-min = <1>;
387 			litex,clkout-divide-max = <126>;
388 			litex,vco-margin = <0>;