Lines Matching +full:divide +full:- +full:10
2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "litex,vexriscv", "litex-dev";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clock-frequency = <100000000>;
25 compatible = "litex,vexriscv-standard", "riscv";
33 #address-cells = <1>;
34 #size-cells = <1>;
38 compatible = "litex,soc-controller";
42 reg-names = "reset",
46 intc0: interrupt-controller@bc0 {
47 compatible = "litex,vexriscv-intc0";
48 #address-cells = <0>;
49 #interrupt-cells = <2>;
50 interrupt-controller;
52 reg-names = "irq_mask", "irq_pending";
53 riscv,max-priority = <7>;
57 interrupt-parent = <&intc0>;
58 interrupts = <2 10>;
67 reg-names =
86 reg-names = "control",
93 #address-cells = <1>;
94 #size-cells = <0>;
97 compatible = "litex,spi-litespi";
105 reg-names = "core_mmap_dummy_bits",
112 #address-cells = <1>;
113 #size-cells = <0>;
115 compatible = "jedec,spi-nor";
117 spi-max-frequency = <10000000>;
122 interrupt-parent = <&intc0>;
134 reg-names =
149 interrupt-parent = <&intc0>;
156 reg-names = "control",
165 compatible = "litex,liteeth-mdio";
169 reg-names = "crg_reset",
172 #address-cells = <1>;
173 #size-cells = <0>;
176 phy0: ethernet-phy@1 {
177 compatible = "ethernet-phy";
183 interrupt-parent = <&intc0>;
200 local-mac-address = [10 e2 d5 00 00 02];
201 reg-names = "rx_slot",
216 phy-handle = <&phy0>;
221 /* DNA data is 57-bits long,
223 In LiteX each 32-bit register holds
227 reg-names = "mem";
233 reg-names = "write", "read";
234 clock-frequency = <I2C_BITRATE_STANDARD>;
235 #address-cells = <1>;
236 #size-cells = <0>;
242 reg-names = "control";
244 port-is-output;
246 gpio-controller;
247 #gpio-cells = <2>;
256 interrupt-parent = <&intc0>;
258 reg-names = "base",
265 gpio-controller;
266 #gpio-cells = <2>;
271 reg-names = "status";
277 reg-names = "enable", "width", "period";
279 #pwm-cells = <2>;
290 interrupt-parent = <&intc0>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 reg-names = "ev_status",
313 interrupt-parent = <&intc0>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 reg-names = "ev_status",
327 clock-outputs {
328 #address-cells = <1>;
329 #size-cells = <0>;
330 clk0: clock-controller@0 {
331 #clock-cells = <1>;
334 clock-output-names = "CLK_0";
335 litex,clock-frequency = <11289600>;
336 litex,clock-phase = <0>;
337 litex,clock-duty-num = <1>;
338 litex,clock-duty-den = <2>;
339 litex,clock-margin = <1>;
340 litex,clock-margin-exp = <2>;
343 clk1: clock-controller@1 {
344 #clock-cells = <1>;
347 clock-output-names = "CLK_1";
348 litex,clock-frequency = <22579200>;
349 litex,clock-phase = <0>;
350 litex,clock-duty-num = <1>;
351 litex,clock-duty-den = <2>;
352 litex,clock-margin = <1>;
353 litex,clock-margin-exp = <2>;
367 reg-names = "drp_reset",
375 #clock-cells = <1>;
377 clock-output-names = "CLK_0", "CLK_1";
378 litex,lock-timeout = <10>;
379 litex,drdy-timeout = <10>;
380 litex,divclk-divide-min = <1>;
381 litex,divclk-divide-max = <107>;
382 litex,clkfbout-mult-min = <2>;
383 litex,clkfbout-mult-max = <65>;
384 litex,vco-freq-min = <600000000>;
385 litex,vco-freq-max = <1200000000>;
386 litex,clkout-divide-min = <1>;
387 litex,clkout-divide-max = <126>;
388 litex,vco-margin = <0>;